Epi Masked Interrupt Status (Epimis) Register, Offset 0X218; Epi Masked Interrupt Status (Epimis) Register [Offset 0X218]; Epi Masked Interrupt Status (Epimis) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 17-35. EPI Raw Interrupt Status (EPIRIS) Register Field Descriptions (continued)
Bit Field
0 ERRRIS

17.11.23 EPI Masked Interrupt Status (EPIMIS) Register, offset 0x218

This register is the masked interrupt status register. On read, it gives the current state of each interrupt
source (read, write, and error) after being masked via the EPIIM register. A write has no effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register, the
interrupt is sent to the interrupt controller.
Figure 17-50. EPI Masked Interrupt Status (EPIMIS) Register [offset 0x218]
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-36. EPI Masked Interrupt Status (EPIMIS) Register Field Descriptions
Bit Field
31-5 Reserved
4 DMAWRMIS
3 DMARDMIS
2 WRMIS
SPRUHE8E – October 2012 – Revised November 2019
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Value Description
Error Raw Interrupt Status
The error interrupt occurs in the following situations:
• WFIFO Full. For a full WFIFO to generate an error interrupt, the WFERR bit in the EPIFIFOLVL
register must be set.
• Read Stalled. For a stalled read to generate an error interrupt, the RSERR bit in the EPIFIFOLVL
register must be set.
• Timeout. If the MAXWAIT field in the EPIGPCFG register is configured to a value other than 0, a
timeout error occurs when iRDY or XFIFO not-ready signals hold a transaction for more than the
count in the MAXWAIT field.
To determine which error occurred, read the status of the EPI Error Interrupt Status and Clear
(EPIEISC) register. This bit is cleared by writing a 1 to the bit in the EPIEISC register that caused
the interrupt.
0 An error has not occurred.
1 A WFIFO Full, a Read Stalled, or a Timeout error has occurred.
Reserved
R-0x0000.000
Value Description
Reserved
Write uDMA Masked Interrupt Status
This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC register.
0 The write uDMA has not completed or the interrupt is masked.
1 The write uDMA has completed and the DMAWRIM bit in the EPIIM register is set, triggering an
interrupt to the interrupt controller.
Read uDMA Masked Interrupt Status
This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC register.
0 The read uDMA has not completed or the interrupt is masked.
1 The read uDMA has completed and the DMAWRIM bit in the EPIIM register is set, triggering an
interrupt to the interrupt controller.
Write Masked Interrupt Status
0 The number of available entries in the WFIFO is above the range specified by the trigger level or
the interrupt is masked.
1 The number of available entries in the WFIFO is within the range specified by the trigger level (the
WRFIFO field in the EPIFIFOLVL register) and the WRIM bit in the EPIIM register is set, triggering
an interrupt to the interrupt controller.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0x0000.000
5
Register Descriptions
4 3 2 1
DMAW DMAR WRMI RDMI
RMIS DMIS S S
R-0 R-0 R-0 R-0
External Peripheral Interface (EPI)
16
0
ERRM
IS
R-0
1297