Epi Raw Interrupt Status (Epiris) Register, Offset 0X214; Epi Raw Interrupt Status (Epiris) Register [Offset 0X214]; Epi Raw Interrupt Status (Epiris) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
Table 17-34. EPI Interrupt Mask (EPIIM) Register Field Descriptions (continued)
Bit Field
0 ERRIM

17.11.22 EPI Raw Interrupt Status (EPIRIS) Register, offset 0x214

This is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A
write has no effect.
Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by
EPIFIFOLVL.
Raw status for error is held until the error is cleared by writing to the EPIEISC register.
Figure 17-49. EPI Raw Interrupt Status (EPIRIS) Register [offset 0x214]
31
15
Reserved
R-0x000
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 17-35. EPI Raw Interrupt Status (EPIRIS) Register Field Descriptions
Bit Field
31-5 Reserved
4 DMAWRRIS
3 DMARDRIS
2 WRRIS
1 RDRIS
1296
External Peripheral Interface (EPI)
Value Description
Error Interrupt Mask
0 ERRIS in the EPIRIS register is masked and does not cause an interrupt.
1 ERRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
Value Description
Reserved
Write uDMA Raw Interrupt Status
0 The write uDMA has not completed.
1 The write uDMA has completed.
Read uDMA Raw Interrupt Status
0 The read uDMA has not completed
1 The read uDMA has completed
Write Raw Interrupt Status
This bit is cleared when the level in the WFIFO is above the trigger point programmed by the
WRFIFO field.
0 The number of available entries in the WFIFO is above the range specified by the WRFIFO field in
the EPIFIFOLVL register.
1 The number of available entries in the WFIFO is within the range specified by the trigger level (the
WRFIFO field in the EPIFIFOLVL register).
Read Raw Interrupt Status
This bit is cleared when the level in the NBRFIFO is below the trigger point programmed by the
RDFIFO field
0 The number of valid entries in the NBRFIFO is below the trigger range specified by the RDFIFO
field in the EPIFIFOLVL register
1 The number of valid entries in the NBRFIFO is in the trigger range specified by the RDFIFO field in
the EPIFIFOLVL register
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0x000
5 4 3 2
DMAW DMAR WRRIS
RRIS DRIS
R-0 R-0 R-1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
RDRIS ERRRIS
R-0 R-0
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