Gpio Port D Data (Gpddat) Register; Gpio Port D Data (Gpddat) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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4.2.7.41 GPIO Port D Data (GPDDAT) Register

The GPIO Port D Data (GPDDAT) register is shown and described in the figure and table below.
31 30
GPIO127 GPIO126
R/W-x R/W-x
23 22
GPIO119 GPIO118
R/W-x R/W-x
15 14
GPIO111 GPIO110
R/W-x R/W-x
7 6
GPIO103 GPIO102
R/W-x R/W-x
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-91. GPIO Port D Data (GPDDAT) Register Field Descriptions
Bit Field
31-0 GPIO127-GPIO96
SPRUHE8E – October 2012 – Revised November 2019
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Figure 4-82. GPIO Port D Data (GPDDAT) Register
29 28
GPIO125 GPIO124
R/W-x R/W-x
21 20
GPIO117 GPIO116
R/W-x R/W-x
13 12
GPIO109 GPIO108
R/W-x R/W-x
5 4
GPIO101 GPIO100
R/W-x R/W-x
Value
Each bit corresponds to one GPIO port D pin (GPIO127-GPIO96)
0 Reading a 0 indicates that the state of the pin is currently low, irrespective of the mode for which
the pin is configured..
Writing a 0 will force an output of 0 if the pin is configured as a GPIO output in the appropriate
GPDMUX1/2 and GPDDIR registers; otherwise, the value is latched but not used to drive the pin.
1 Reading a 1 indicates that the state of the pin is currently high irrespective of the mode for which
the pin is configured.
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPDMUX1
and GPDDIR registers; otherwise, the value is latched but not used to drive the pin.
Copyright © 2012–2019, Texas Instruments Incorporated
C28 General-Purpose Input/Output (GPIO)
27 26
GPIO123 GPIO122
R/W-x R/W-x
19 18
GPIO115 GPIO114
R/W-x R/W-x
11 10
GPIO107 GPIO106
R/W-x R/W-x
3 2
GPIO99 GPIO98
R/W-x R/W-x
Description
General-Purpose Input/Output (GPIO)
25 24
GPIO121 GPIO120
R/W-x R/W-x
17 16
GPIO113 GPIO112
R/W-x R/W-x
9 8
GPIO105 GPIO104
R/W-x R/W-x
1 0
GPIO97 GPIO96
R/W-x R/W-x
449