C28 Cpu Timer 2 Clock Configuration (Clkctl) Register; Peripheral Clock Control Register 0 (Pclkcr0); C28 Cpu Timer 2 Clock Configuration (Clkctl) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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1.13.7.29 C28 CPU Timer 2 Clock Configuration (CLKCTL) Register

Figure 1-124. C28 CPU Timer 2 Clock Configuration (CLKCTL) Register
15
7
TMR2CLKPRESCALE
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-135. C28 CPU Timer 2 Clock Configuration (CLKCTL) Register Field Descriptions
Bit Field
15-8 Reserved
7-5 TMR2CLKPRES
CALE
4-3 TMR2CLKSRCS
EL
2-0 Reserved

1.13.7.30 Peripheral Clock Control Register 0 (PCLKCR0)

15
Reserved
R-0:0
7
Reserved
R-0:0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
SPRUHE8E – October 2012 – Revised November 2019
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5 4
TMR2CLKSRCSEL
Value Description
Reserved
Timer2 Clock Prescale Select
These bits select the pre-scale value for the selected clock source for CPU Timer 2.
This selection is not affected by the missing clock detect circuit.
0,0,0 /1 (default on reset)
0,0,1 /2
0,1,0 /4
0,1,1 /8
1,0,0 /16
1,0,1 Reserved
1,1,0 Reserved
1,1,1 Reserved
Timer2 Clock Source Select
This bit selects the source for C28 CPU Timer 2.
This selection is not affected by the missing clock detect circuit.
00 C28 SYSCLK selected (default on reset, pre-scaler is bypassed)
01 External oscillator (X1) selected
10 OSCCLK selected
11 Reserved
Reserved
Figure 1-125. Peripheral Clock Control Register 0 (PCLKCR0)
13 12
MCBSPAENCLK
R/W-0
5 4
I2CAENCLK
R/W-0
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
3 2
R/W-0
11 10
Reserved SCIAENCLK
R-0 R/W-0
3 2
Reserved TBCLKSYNC
R-0:0 R/W-0
System Control Registers
8
0
Reserved
R-0:0
9 8
Reserved SPIAENCLK
R-0:0 R/W-0
1 0
Reserved HRPWMENCLK
R-0 R/W-0
System Control and Interrupts
249