Cx Shram Configuration Register 4 (Cxsrcr4); Cx Shram Configuration Register 4 (Cxsrcr4) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
Table 5-16. Cx SHRAM Configuration Register 3 (CxSRCR3) Field Descriptions (continued)
Bit Field
17 DMAWRPROTC12
16 FETCHPROTC12
15-11 Reserved
10 CPUWRPROTC11
9 DMAWRPROTC11
8 FETCHPROTC11
7-3 Reserved
2 CPUWRPROTC10
1 DMAWRPROTC10
0 FETCHPROTC10
5.2.1.5 Cx SHRAM Config Register 4 (CxSRCR4)
31
23
15
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-17. Cx SHRAM Configuration Register 4 (CxSRCR4) Field Descriptions
Bit Field
31-11 Reserved
10 CPUWRPROTC15
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Value Description
0 M3 uDMA Write allowed to C12 RAM Block.
1 M3 uDMA Write not allowed to C12 RAM Block.
0 M3 CPU Fetch allowed from C12 RAM Block.
1 M3 CPU Fetch not allowed from C12 RAM Block.
Reserved
0 M3 CPU Write allowed to C11 RAM Block.
1 M3 CPU Write not allowed to C11 RAM Block.
0 M3 uDMA Write allowed to C11 RAM Block.
1 M3 uDMA Write not allowed to C11 RAM Block.
0 M3 CPU Fetch allowed from C11 RAM Block.
1 M3 CPU Fetch not allowed from C11 RAM Block.
Reserved
0 M3 CPU Write allowed to C10 RAM Block.
1 M3 CPU Write not allowed to C10 RAM Block
0 M3 uDMA Write allowed to C10 RAM Block.
1 M3 uDMA Write not allowed to C10 RAM Block.
0 M3 CPU Fetch allowed from C10 RAM Block.
1 M3 CPU Fetch not allowed from C10 RAM Block.
Figure 5-8. Cx SHRAM Configuration Register 4 (CxSRCR4)
Reserved
Reserved
Reserved
R-0
Reserved
R-0
Value Description
Reserved
0 M3 CPU Write allowed to C15 RAM Block.
1 M3 CPU Write not allowed to C15 RAM Block.
Copyright © 2012–2019, Texas Instruments Incorporated
R-0
R-0
11 10
CPUWRPROT
C15
R/W-0
3 2
CPUWRPROT
C14
R/W-0
RAM Control Module Registers
24
16
9 8
DMAWRPROT FETCHPROTC
C15 15
R/W-0 R/W-0
1 0
DMAWRPROT FETCHPROTC
C14 14
R/W-0 R/W-0
Internal Memory
479