Control Subsystem Ipc Registers; M3 Clock Semaphore Register; Ctomipcset Register; M3 Flash Semaphore Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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System Control Registers

NOTE: If simultaneous write access is performed to the above registers and a conflict occurs, the

M3 will be given priority.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

1.13.12 Control Subsystem IPC Registers

The registers below are mapped to the control subsystem address map only.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

System Control and Interrupts

Figure 1-170. M3 Clock Semaphore Register

Table 1-182. M3 Flash Semaphore Field Descriptions

Writing the value 0xB95C813 will allow writes to the SEM bits or writes are ignored. Reads will

Note: This is to prevent spurious writes to the semaphore bits.

• A value of "00", "10", "11" gives ownership to the M3

• A value of "01" gives ownership to the C28.

• The following are the only state transitions allowed on these bits.

"00","11" -> "01"

"00","11" -> "10"

• "10" -> "00","11" (This can only happen from an M3 write to these bits to relinquish its ownership)

• State transitions from "00" → "11" and "11" → "00" are allowed by design. However these

transitions will not result in change in ownership.

Figure 1-171. CTOMIPCSET Register

SPRUHE8E – October 2012 – Revised November 2019

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