C-Boot Rom Exceptions Handling - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Exception Event Source
CLOCKFAIL – from missing
clock detection logic
M3BISTERR
C28BISTERR
C28RAMUNCERR
C28FLUNCERR
ACIBERR
ILLEGAL
PIE VECTOR ADDRESS
MISMATCH
SPRUHE8E – October 2012 – Revised November 2019
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Table 6-23. C-Boot ROM Exceptions Handling
Description
CLKFAIL condition detected
M3 HW BIST Error NMI Flag
C28 HW BIST Error NMI Flag
C28 RAM Uncorrectable Error
NMI Flag
C28 Flash Uncorrectable Error
NMI
CIB Error NMI Flag
ITRAP exception
PIE vector fetch mismatch
handler at 0x3FFFBE
Copyright © 2012–2019, Texas Instruments Incorporated
C-Boot ROM action
cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register bits
and returns from the interrupt
handler.
NMI is generated to the master
subsystem also, No IPC
message is sent.
Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to C28 also, so no
need to send an IPC message.
Default NMI HANDLER:->
Clear NMI Flags, Save error
status in CTOMBOOTSTS
register bits and wait in
while(1) loop for master to
handle the error state. NMI is
generated to M3 also, so no
need to send an IPC message.
cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register,
send IPC message to master
and wait in while(1) loop for
master to handle the error
state..
cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register,
send IPC message to master
and wait in while(1) loop for
master to handle the error state
cbrom_handle_nmi :-> Clear
NMI Flags, Save error status in
CTOMBOOTSTS register bits
and wait in while(1) loop for
master to handle the error
state.
NMI is generated to M3 also,
so no need to send an IPC
message.
cbrom_itrap_isr :-> IPC
Message is sent to master and
iTrap address is written to
CTOMIPCADDR.
CTOMBOOTSTS register is set
to reflect the error status and
wait in while(1) loop for master
to handle the error state.
Update CTOMBOOTSTS to
reflect the error, and the ROM
handler @0x3FFFBE will send
an IPC message to master and
wait in while(1) loop for master
to handle the error state.
ROM Code and Peripheral Booting
C-Boot ROM Description
C-Boot ROM state after
exception
Continue to boot, because
missing clock circuit will switch
CPU to 10 MHz clock source
Wait in While(1) loop, for reset
from master.
Wait in While(1) loop, for reset
from master.
Wait in While(1) loop, for reset
frommaster.
Wait in While(1) loop, for reset
frommaster.
Wait in While(1) loop, for reset
from master.
Wait in While(1) loop, for reset
frommaster.
Wait in While(1) loop, for reset
from master.
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