Xpll Clkout Control (Xpllclkcfg) Register; Usb Pll Configuration (Upllctl) Register; Master Subsystem Clock Divider (M3Ssdivsel) Register Field Descriptions; Xpll Clkout Control (Xpllclkcfg) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-110. Master Subsystem Clock Divider (M3SSDIVSEL) Register Field Descriptions
Bit Field
31-2 Reserved
1-0 M3SSDIVSEL

1.13.7.5 XPLL CLKOUT Control (XPLLCLKCFG) Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-111. XPLL CLKOUT Control (XPLLCLKCFG) Register Field Descriptions
Bit Field
31-2 Reserved
1-0 XPLLCLKOUTDI
V

1.13.7.6 USB PLL Configuration (UPLLCTL) Register

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-112. USB PLL Configuration (UPLLCTL) Register Field Descriptions
Bit Field
31-3 Reserved
2 UPLLCLKEN
228
System Control and Interrupts
Value Description
Reserved
M3 Subsystem Clock Divide
This bit selects between /4, /2, and /1 for the M3 sub-system clock. The C28 CLKIN clock is divided
by the below ratios to generate the M3 SS clock. The configuration of the M3SSDIVSEL bits is as
follows.
00 Select M3SS clock divide By 1 of PLLYSCLK clock
01 Select M3SS clock divide By 2 of PLLYSCLK clock
10 Select M3SS clock divide By 4 of PLLSYSCLK clock
11 Reserved
Figure 1-100. XPLL CLKOUT Control (XPLLCLKCFG) Register
Reserved
R-0:0
Value Description
Reserved
XPLLCLKOUT Divide Ratio
This bit selects a clock divide ratio for the XPLLCLKOUT clock. The configuration of the
XPLLCLKOUTDIV bits is as follows.
00 XPLLCLKOUT is off
01 Select XPLLCLKOUT = SYSCLK/4
10 Select XPLLCLKOUT = M3 SSCLK/4
11 Select XPLLCLKOUT = PLLSYSCLK/4 (default)
Figure 1-101. USB PLL Configuration (UPLLCTL) Register
Reserved
R-0:0
Value Description
Reserved
USB PLL Clock Enable
USB PLL bypassed or included in the USB clock path.
This bit decides if the USB PLL is bypassed to supply the 60-MHz clock to the USB
Note: The PLL bypass option can be used only with GPIO_XCLKIN as a clock source to the USB
because the oscillators will support only up to a 20 MHz input clock
0 USB PLL is bypassed; clock to the USB is direct feed from GPIO_XCLKIN.
1 USB PLL is on the clock path to USBCLK and it is the PLL multiplied clock.
Copyright © 2012–2019, Texas Instruments Incorporated
3 2
UPLLCLKEN
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
2 1 0
XPLLCLKOUTDIV
R/W-11
1 0
UPLLEN
R/W-0 R/W-0
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