Gpio Alternate Function Select (Gpioafsel) Register; Gpio Alternate Function Select (Gpioafsel) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.6.10 GPIO Alternate Function Select (GPIOAFSEL) Register, offset 0x420
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a GPIO
and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO
line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on
each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions.
NOTE: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0. A Power-On-Reset POR or asserting XRS
puts the pins back to their default state.
It is possible to create a software sequence that prevents the debugger from
connecting to the microcontroller. If the program code loaded into flash
immediately changes the JTAG pins to their GPIO functionality, the debugger
may not have enough time to connect and halt the controller before the JTAG
pin functionality switches. As a result, the debugger may be locked out of the
part. This issue can be avoided with a software routine that restores JTAG
functionality based on an external or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of critical
hardware peripherals. Protection is provided for the NMI pin (PB7). Writes to protected bits of the GPIO
Alternate Function Select (GPIOAFSEL) register, GPIO Pull Up Select (GPIOPUR) register, GPIO Core
Select (GPIOCSEL) register, and GPIO Digital Enable (GPIODEN) register are not committed to storage
unless the GPIO Lock (GPIOLOCK) register has been unlocked and the appropriate bits of the GPIO
Commit (GPIOCR) register have been set.
When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock and data
pins, the pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register (see
examples in Section
Figure 4-13. GPIO Alternate Function Select (GPIOAFSEL) Register
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-14. GPIO Alternate Function Select (GPIOAFSEL) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 AFSEL
362
General-Purpose Input/Output (GPIO)
4.1.4).
R-0
Value Description
Reserved
GPIO Alternate Function Select
0 The associated pin functions as a GPIO and is controlled by the GPIO registers.
1 The associated pin functions as a peripheral signal and is controlled by the alternate hardware
function.
Copyright © 2012–2019, Texas Instruments Incorporated
CAUTION
Reserved
R-0
8 7
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
AFSEL
R/W-0
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