Event-Trigger Flag Register (Etflg); Event-Trigger Flag Register (Etflg) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Table 7-87. Event-Trigger SOC Pre-Scale Register (ETSOCPS) Field Descriptions (continued)
Bit Field
7-4 SOCACNT2
3-0 SOCAPRD2
15
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-88. Event-Trigger Flag Register (ETFLG) Field Descriptions
Bit Field
15-4 Reserved
3 SOCB
2 SOCA
1 Reserved
0 INT
822
C28 Enhanced Pulse Width Modulator (ePWM) Module
Value Description
EPWMxSOCA Counter 2
When ETPS[SOCPSSEL] = 1, these bits indicate how many selected events have occurred:
0000 No events
0001 1 event
0010 2 events
0011 3 events
0100 4 events
. . . . . .
1111 15 events
EPWMxSOCA Period 2 Select
When ETPS[SOCPSSEL] = 1, these bits select how many selected event need to occur before an
SOCA pulse is generated:
0000 Disable counter
0001 Generate interrupt on SOCACNT2 = 1 (first event)
0010 Generate interrupt on SOCACNT2 = 2 (second event)
0011 Generate interrupt on SOCACNT2 = 3 (third event)
0100 Generate interrupt on SOCACNT2 = 4 (fourth event)
. . . . . .
1111 Generate interrupt on SOCACNT2 = 15 (fifteenth event)
Figure 7-136. Event-Trigger Flag Register (ETFLG)
4
R-0
Value Description
Reserved
Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag
0 Indicates no EPWMxSOCB event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB
output will continue to be generated even if the flag bit is set.
Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag
Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit is
set.
0 Indicates no event occurred
1 Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA
output will continue to be generated even if the flag bit is set.
Reserved
Latched ePWM Interrupt (EPWMx_INT) Status Flag
0 Indicates no event occurred
1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated. No further interrupts will be
generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit
is still set. If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared.
Refer to Figure 7-44.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
SOCB SOCA
R-0 R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
8
1 0
Reserved INT
R-0 R-0
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