Run Mode Clock Gating Control Register 2 (Rcgc2); Run Mode Clock Gating Control Register 2 (Rcgc2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-124. Deep Sleep Mode Clock Gating Control Register 1 (DCGC1) Field Descriptions (continued)
Bit Field
6 SSI2
5 SSI1
4 SSI0
3 UART3
2 UART2
1 UART1
0 UART0

1.13.7.19 Run Mode Clock Gating Control Register 2 (RCGC2)

Figure 1-114. Run Mode Clock Gating Control Register 2 (RCGC2)
31
Reserved
R-0
23 22
15 14
Reserved
R-0
7 6
GPIOH GPIOG
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-125. Run Mode Clock Gating Control Register 2 (RCGC2) Field Descriptions
Bit Field
31-29 Reserved
28 EMAC0
27-17 Reserved
238
System Control and Interrupts
Value Description
SSI2 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the SSI2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
SSI1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the SSI1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
SSI0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the SSI0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART3 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the UART3 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART2 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the UART2 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART1 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the UART1 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
UART0 Clock Gating Control in Deep Sleep Mode
This bit controls the clock gating for the UART0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
29 28
EMAC0
R/W-0
21 20
Reserved
R-0
13 12
µDMA
R/W-0
5 4
GPIOF GPIOE
R/W-0 R/W-0
Value Description
Reserved
EMAC0 Clock Gating Control in Run Mode
This bit controls the clock gating for the EMAC0 module. If set, the module receives a clock and
functions. Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the
module generates bus faults.
Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
27
Reserved
R-0
19 18
Reserved
R-0
3 2
GPIOD GPIOC
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
24
17 16
USB
R/W-0
9 8
GPIOJ
R/W-0
1 0
GPIOB GPIOA
R/W-0 R/W-0
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