Interrupt 32-63 Set Pending (Pend1) Register; Interrupt 64-95 Set Pending (Pend2) Register; Interrupt 32-63 Set Pending (Pend1) Register Field Descriptions; Interrupt 64-95 Set Pending (Pend2) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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25.5.12 Interrupt 32-63 Set Pending (PEND1) Register, offset 0x204
The Interrupt 32-63 Set Pending (PEND1) register forces interrupts into the pending state and shows
which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 31 corresponds to Interrupt 63. See the
Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-22. Interrupt 32-63 Set Pending (PEND1) Register Field Descriptions
Bit Field
31-0 INT
25.5.13 Interrupt 64-95 Set Pending (PEND2) Register, offset 0x208
The Interrupt 64-95 Set Pending (PEND2) register forces interrupts into the pending state and shows
which interrupts are pending. Bit 0 corresponds to Interrupt 64; bit 31 corresponds to Interrupt 95. See the
Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25-23. Interrupt 64-95 Set Pending (PEND2) Register Field Descriptions
Bit Field
31-0 INT
25.5.14 Interrupt 96-127 Set Pending (PEND3) Register, offset 0x20C
The Interrupt 96-127 Set Pending (PEND3) register forces interrupts into the pending state and shows
which interrupts are pending. Bit 0 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. See
the Cortex-M3 Processor chapter for interrupt assignments.
Note: This register can only be accessed from privileged mode.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 25-16. Interrupt 32-63 Set Pending (PEND1) Register
Value Description
Interrupt Set Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to
pending even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be
cleared by setting the corresponding INT[n] bit in the UNPEND1 register.
Figure 25-17. Interrupt 64-95 Set Pending (PEND2) Register
Value Description
Interrupt Set Pending
0 On a read, indicates that the interrupt is not pending. On a write, no effect.
1 On a read, indicates that the interrupt is pending. On a write, the corresponding interrupt is set to
pending even if it is disabled.
If the corresponding interrupt is already pending, setting a bit has no effect. A bit can only be
cleared by setting the corresponding INT[n] bit in the UNPEND2 register.
Copyright © 2012–2019, Texas Instruments Incorporated
INT
R/W-0
INT
R/W-0
NVIC Register Descriptions
0
0
1655
Cortex-M3 Peripherals