Event-Trigger Counter Initialization Control Register (Etcntinitctl); Event-Trigger Counter Initialization Register (Etcntinit); Event-Trigger Counter Initialization Control Register (Etcntinitctl) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Registers
Figure 7-139. Event-Trigger Counter Initialization Control Register (ETCNTINITCTL)
15 14
SOCBINITEN SOCAINITEN
R/W-0 R/W-0
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-91. Event-Trigger Counter Initialization Control Register (ETCNTINITCTL) Field
Bit Field
15 SOCBINITEN
14 SOCAINITEN
13 INTINITEN
12 SOCBINITFRC
11 SOCAINITFRC
10 INTINITFRC
9-0 Reserved
Figure 7-140. Event-Trigger Counter Initialization Register (ETCNTINIT)
15
Reserved
7
SOCAINIT
R/W-0:00
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
824
C28 Enhanced Pulse Width Modulator (ePWM) Module
13 12
INTINITEN SOCBINITFRC
R/W-0 R/W-0
Value Description
EPWMxSOCB Counter 2 Initialization Enable
0 Has no effect.
1 Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC
event or software force.
EPWMxSOCA Counter 2 Initialization Enable
0 Has no effect.
1 Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC
event or software force.
EPWMxINT Counter 2 Initialization Enable
0 Has no effect.
1 Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC
event or software force.
EPWMxSOCB Counter 2 Initialization Force
0 Has no effect.
1 This bit forces the ET EPWMxSOCB counter to be initialized with the contents of
ETCNTINIT[SOCBINIT].
EPWMxSOCA Counter 2 Initialization Force
0 Has no effect.
1 This bit forces the ET EPWMxSOCA counter to be initialized with the contents of
ETCNTINIT[SOCAINIT].
EPWMxINT Counter 2 Initialization Force
0 Has no effect.
1 This bit forces the ET EPWMxINT counter to be initialized with the contents of
ETCNTINIT[INTINIT].
Reserved
12
R-0:00
4
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
SOCAINITFRC INTINITFRC
R/W-0 R/W-0
Reserved
R-0:00
Descriptions
11
3
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
9
Reserved
R-0:00
SOCBINIT
R/W-0:00
INTINIT
R/W-0:00
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8
0
8
0