Usb Vbus Droop Control Register (Usbvdc); Usb Vbus Droop Control Register (Usbvdc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
18.5.55 USB VBUS Droop Control Register (USBVDC), offset 0x430
The USB VBUS droop control 32-bit register (USBVDC) enables a controlled masking of VBUS to
compensate for any in-rush current by a Device that is connected to the Host controller. The in-rush
current can cause VBUS to droop, causing the USB controller's behavior to be unexpected. The USB Host
controller allows VBUS to fall lower than the VBUS Valid level (4.75 V) but not below AValid (2.0 V) for 65
microseconds without signaling a VBUSERR interrupt in the controller. Without this, any glitch on VBUS
would force the USB Host controller to remove power from VBUS and then re-enumerate the Device.
Mode(s): OTG A or Host
USBVDC is shown in
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18-71. USB VBUS Droop Control Register (USBVDC) Field Descriptions
Bit Field Value
31-1 Reserved 0
0 VBDEN
0
1
1406
M3 Universal Serial Bus (USB) Controller
Figure 18-66 and described in
Figure 18-66. USB VBUS Droop Control Register (USBVDC)
Reserved
R-0
Description
Reserved. Reset is 0x0000.000.
VBUS Droop Enable
No effect
Any changes from VBUSVALID are masked when VBUS goes below 4.75 V but not lower than 2.0 V for
65 microseconds. During this time, the VBUS state indicates VBUSVALID.
Copyright © 2012–2019, Texas Instruments Incorporated
Table 18-71.
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
0
VBDEN
R/W-0
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