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Register Descriptions
17.11.15 EPI Status (EPISTAT) Register, offset 0x060
This register indicates which non-blocking read register is currently active; it also indicates whether the
external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read,
as the bus would be blocked and as a result, this register could not be accessed).
This register is useful to determine which non-blocking read register is active when both are loaded with
values and when implementing sequencing or sharing.
This register is also useful when canceling non-blocking reads, as it shows how many values were read by
the canceled side.
31
15
7
6
XFEMPTY
INITSEQ
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
Field
31-10
Reserved
9
CELOW
8
XFFULL
7
XFEMPTY
6
INITSEQ
5
WBUSY
1290
External Peripheral Interface (EPI)
Figure 17-42. EPI Status (EPISTAT) Register [offset 0x060]
Reserved
R-0x0000.00
5
4
WBUSY
NBRBUSY
R-0
R-0
Table 17-28. EPI Status (EPISTAT) Register Field Descriptions
Value
Description
Reserved
Clock Enable Low
This bit provides information on the clock status when in general-purpose mode and the RDYEN bit
is set.
0
The external device is not gating the clock.
1
The external device is gating the clock (iRDY is low). Attempts to read or write in this situation are
stalled until the clock is enabled or the counter times out as specified by the MAXWAIT field.
External FIFO Full
This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode
with the XFFEN bit set in the EPIHBnCFG register. The EPI0S26 signal reflects the status of this
bit.
0
The external device is not gating the clock.
1
The XFIFO is signaling as full (the FIFO full signal is high). Attempts to write in this case are stalled
until the XFIFO full signal goes low or the counter times out as specified by the MAXWAIT field.
External FIFO Empty
This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode
with the XFEEN bit set in the EPIHBnCFG register. The EPI0S27 signal reflects the status of this
bit.
0
The external device is not gating the clock.
1
The XFIFO is signaling as empty (the FIFO empty signal is high). Attempts to read in this case are
stalled until the XFIFO empty signal goes low or the counter times out as specified by the
MAXWAIT field.
Initialization Sequence
0
The SDRAM interface is not in the wakeup period.
1
The SDRAM interface is running through the wakeup period (greater than 100 μs). If an attempt is
made to read or write the SDRAM during this period, the access is held off until the wakeup period
is complete.
Write Busy
0
The external interface is not performing a write.
1
The external interface is performing a write.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0x0000.00
3
Reserved
R-0x0
SPRUHE8E – October 2012 – Revised November 2019
10
9
CELOW
R-0
1
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16
8
XFFULL
R-0
0
ACTIVE
R-0
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