System Control Registers; System Control, Configuration Register Map; System Control, Configuration Registers Address Map - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers

1.13 System Control Registers
This section provides details of all the system control module registers that let users configure, control,
and monitor various functions and features in the device.
Section 1.13.1 and
the reset source for each register and whether the register is accessible by the master subsystem or
control subsystem or both. The below Register Map also provides details on whether the register is write
protected and if the register is read-only.
Registers accessible by only the Cortext-M3 CPU in the master subsystem have only M3 "base
address+offset" and registers accessible by only the C28x CPU in the control subsystem have only C28x
"base address+offset" associated with it. The registers which are accessible by both have both M3 CPU
and C28x CPU "base address + offset".
The "Write Once" or "Write = 1" in the Read-Only column of the below table means that the respective
LOCK registers can be written only once and can only set the bits in the respective registers to "1." Writes
of "0" are ignored and once set to "1" cannot be written again until the respective reset is generated to
reset the state of the LOCK configuration.
Note that all the addresses in the memory map which are not defined in the below table are reserved.
None of the reserved addresses, nor any of the reserved bits in registers should be written to. If there is a
need to write to them they should be written back with the same bit value as read from them.

1.13.1 System Control, Configuration Register Map

Table 1-38. System Control, Configuration Registers Address Map
Register Register
Acronym Description
Master Subsystem Device Identification and
System Control Registers:
Device Identification
DID0
Register 0
Device Identification
DID1
Register 1
Device Configuration
DC1
1 Register
Device Configuration
DC2
2 Register
Device Configuration
DC4
4 Register
Device Configuration
DC6
6 Register
Device Configuration
DC7
7 Register
Software Reset
SRCR0
Control Register 0
Software Reset
SRCR1
Control Register 1
Software Reset
SRCR2
Control Register 2
Software Reset
SRCR3
Control Register 3
Master Reset Cause
MRESC
Register
Run Mode Clock
RCC Configuration
Register
Master GPIO High
GPIOHBCTL Performance Bus
Control Register
Run Mode Clock
RCGC0 Gating Control
Register 0
166
System Control and Interrupts
Table 1-38 give details about the "base address+offset" of each register and identifies
C28
Offset M3 Offset
Size (x8) (x16)
0x400F:E0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Copyright © 2012–2019, Texas Instruments Incorporated
C28
Protectio M3
(x8) n Protection
00
0x0
0x4
0x10
0x14 MWRALLOW
0x1C MWRALLOW
0x24 MWRALLOW
0x28
0x40 MWRALLOW
0x44 MWRALLOW
0x48 MWRALLOW
0x4C MWRALLOW
0x5C
0x060 MWRALLOW
0x6C MWRALLOW
0x100 MWRALLOW
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Read
Reset Source Only
XRS
M3SYSRST Yes
XRS
XRS Yes
XRS Yes
XRS Yes
XRS
M3SYSRST
M3SYSRST
M3SYSRST
M3SYSRST
POR
M3SYSRST
M3SYSRST
M3SYSRST
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