Acib And Analog Peripherals Clocking; Configuring Xclkout - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Clock Control
subsystem can set the SEM bits back to "0,0" or "1,1".
As explained above, it must be noted that the SEM bits in the CCLKREQUEST register can only be set to
"0,1" when the current state of the SEM bits are either "0,0" or "1,1". Also the SEM bits in the
MCLKREQUEST register can only be set to "1,0" when the current state of the SEM bits are either "0,0"
or "1,1".

1.8.6 ACIB and Analog Peripherals Clocking

The ACIB and analog peripherals that are accessible through the ACIB are clocked by the PLLSYSCLK
divided by the divider configured in the CCLKCTL register. As shown in
to as ASYSCLK.
Only the control subsystem can configure the divider in the CCLKCTL register. Refer to the device data
manual for more details on the ASYSCLK MIN/MAX requirements. To configure the clock for the analog
subsystem, it is advised that the user call the TI-provided function in C-OTP (control subsystem OTP, refer
to the memory map of this device). This function is explained in TI-provided analog OTP functions in the
Analog Subsystem chapter. It is advised that this function is called with a proper divider value as a
parameter based on user clock configuration requirements on the device during the application
initialization process.
1.8.6.1 MCIBSTATUS and CCIBSTATUS
Both the master subsystem and control subsystem can monitor the status of the ACIB by looking at these
registers. The CIBBUSCLKCNT bits (8-15) of both the MCIBSTATUS and CCIBSTATUS registers are
incremented by the ASYSCLK. Users can use this counter to know if the ACIB is functional.
Bit 0 (APGOODSTS) of both these registers shows the status of the analog subsystem's power.
Bits 1 and 2 (READY and INTS bits) show the state of the ACIB READY and ACIB INTS signals which
can be monitored for what caused an ACIBERR error.
The INTS signal will be stuck if there is no response on any of the analog peripheral interrupt lines that
are connected through the ACIB. The READY signal will also be stuck if any of the reads/writes do not go
through the ACIB.

1.8.7 Configuring XCLKOUT

To aid in debugging of the master subsystem and control subsystem, PF2_GPIO34 can be configured for
XCLKOUT operation. Refer to the GPIOs chapter of this document on how to configure this GPIO for
XCLKOUT operation.
XCLKOUT on this device is either PLLSYSCLK, M3SSCLK, or C28SYSCLK as chosen by the
XPLLCLKOUTDIV bits set in the XPLLCLKCFG register as shown in
master subsystem can configure the XCLKOUT divider. Refer to the XPLLCLKCFG and CXCLK register
descriptions for more details.
136
System Control and Interrupts
Copyright © 2012–2019, Texas Instruments Incorporated
Figure 1-12, this clock is referred
Figure 1-12. Note that only the
SPRUHE8E – October 2012 – Revised November 2019
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