Gpio Pad Configuration Examples - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
4.1.4 Initialization and Configuration
The GPIO modules may be accessed via two different memory apertures. The legacy aperture, the
Advanced Peripheral Bus (APB), is backwards-compatible with existing software. The other aperture, the
Advanced High-Performance Bus (AHB), offers the same register map but provides better back-to-back
access performance than the APB bus. These apertures are mutually exclusive. The aperture enabled for
a given GPIO port is controlled by the appropriate bit in the GPIOHBCTL register.
To use the pins in a particular GPIO port, the clock for the port must be enabled by setting the appropriate
GPIO Port bit field (GPIOn) in the RCGC2 register.
On reset, all GPIO pins are configured to be undriven (tri-state): GPIOAFSEL=0, GPIODEN=0 and
GPIOPUR=0. Table 4-2
settings required to achieve them.
GPIO port.
It is recommended to configure the GPIOPCTL register before configuring the GPIOAFSEL register.
For example (referring to the ControlSuite UART examples), the recommended configuration procedure
for UART is as follows:
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
rather than:
GPIOPinTypeUART(GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1);
GPIOPinConfigure(GPIO_PA0_U0RX);
GPIOPinConfigure(GPIO_PA1_U0TX);
While the latter one would work without any problem on REV0, the behavior changed as described below
from REVA onward.
On F28M35x REV0 – if user selects GPIOAFSEL with GPIOPCTL=0, then the respective IO is tri-stated.
On F28M35x REVA/B– if user selects GPIOAFSEL with GPIOPCTL=0, then the respective IO is driven
LOW.
Configuratio
n
AFSEL
Digital Input
(GPIO)
Digital Output
(GPIO)
Open Drain
Output (GPIO)
Open Drain
Input/Output
(I2C)
Digital Input
(Timer CCP)
Digital Output
(Timer PWM)
Digital
Input/Output
(SSI)
Digital
Input/Output
(UART)
(1)
X=Ignored (don't care bit); ?=Can be either 0 or 1, depending on the configuration
354
General-Purpose Input/Output (GPIO)
shows all possible configurations of the GPIO pads and the control register
Table 4-3
Table 4-2. GPIO Pad Configuration Examples
DIR ODR
0 0
0 1
0 1
1 X
1 X
1 X
1 X
1 X
Copyright © 2012–2019, Texas Instruments Incorporated
shows how a rising edge interrupt is configured for pin 2 of a
(1)
GPIO Register Bit Value
DEN PUR
0 1
0 1
1 1
1 1
0 1
0 1
0 1
0 1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
CSEL APSEL
? 0
? 0
X 0
X 0
? 0
? 0
? 0
? 0
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0
0
0
?
0
0
?
?