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14.2.3 Operating Modes
The I2C module has four basic operating modes to support data transfers as a master and as a slave.
See
Table 14-1
for the names and descriptions of the modes.
If the I2C module is a master, it begins as a master-transmitter and typically transmits an address for a
particular slave. When giving data to the slave, the I2C module must remain a master-transmitter. To
receive data from a slave, the I2C module must be changed to the master-receiver mode.
If the I2C module is a slave, it begins as a slave-receiver and typically sends acknowledgment when it
recognizes its slave address from a master. If the master will be sending data to the I2C module, the
module must remain a slave-receiver. If the master has requested data from the I2C module, the module
must be changed to the slave-transmitter mode.
Operating Mode
Slave-receiver modes
Slave-transmitter mode
Master-receiver mode
Master-transmitter modes
SPRUHE8E – October 2012 – Revised November 2019
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Figure 14-4. Bit Transfer on the I2C-Bus
Data line
stable data
SDA
SCL
Table 14-1. Operating Modes of the I2C Module
Description
The I2C module is a slave and receives data from a master.
All slaves begin in this mode. In this mode, serial data bits received on SDA are shifted in with
the clock pulses that are generated by the master. As a slave, the I2C module does not
generate the clock signal, but it can hold SCL low while the intervention of the device is
required (RSFULL = 1 in I2CSTR) after a byte has been received. See section
for more details.
The I2C module is a slave and transmits data to a master.
This mode can be entered only from the slave-receiver mode; the I2C module must first receive
a command from the master. When you are using any of the 7-bit/10-bit addressing formats,
the I2C module enters its slave-transmitter mode if the slave address byte is the same as its
own address (in I2COAR) and the master has transmitted R/W = 1. As a slave-transmitter, the
I2C module then shifts the serial data out on SDA with the clock pulses that are generated by
the master. While a slave, the I2C module does not generate the clock signal, but it can hold
SCL low while the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has
been transmitted. See section
The I2C module is a master and receives data from a slave.
This mode can be entered only from the master-transmitter mode; the I2C module must first
transmit a command to the slave. When you are using any of the 7-bit/10-bit addressing
formats, the I2C module enters its master-receiver mode after transmitting the slave address
byte and R/W = 1. Serial data bits on SDA are shifted into the I2C module with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (RSFULL = 1 in I2CSTR) after a byte has been
received.
The IC module is a master and transmits control information and data to a slave.
All masters begin in this mode. In this mode, data assembled in any of the 7-bit/10-bit
addressing formats is shifted out on SDA. The bit shifting is synchronized with the clock pulses
generated by the I2C module on SCL. The clock pulses are inhibited and SCL is held low when
the intervention of the device is required (XSMT = 0 in I2CSTR) after a byte has been
transmitted.
Copyright © 2012–2019, Texas Instruments Incorporated
I2C Module Operational Details
Change of data
allowed
Section 14.2.7
for more details.
C28 Inter-Integrated Circuit Module
Section 14.2.7
1049
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