Transmit Control Registers (Xcr1 And Xcr2); Frame Length Formula For Receive Control 2 Register (Rcr2) - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 15-76. Receive Control Register 2 (RCR2) Field Descriptions (continued)
Bit Field Value
7-5 RWDLEN2 0-7h
0
1h
2h
3h
4h
5h
6h-7h
4-3 RCOMPAND 0-3h
0
1h
2h
3h
2 RFIG
0
1
1-0 RDATDLY 0-3h
0
1h
2h
3h
Table 15-77. Frame Length Formula for Receive Control 2 Register (RCR2)
RPHASE
0 0 ≤ RFRLEN1 ≤ 127
1 0 ≤ RFRLEN1 ≤ 127

15.12.6 Transmit Control Registers (XCR1 and XCR2)

Each McBSP has two transmit control registers, XCR1
registers enable you to:
SPRUHE8E – October 2012 – Revised November 2019
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Description
Receive word length 2. Each frame of receive data can have one or two phases, depending on the
value that you load into the RPHASE bit. If a single-phase frame is selected, RWDLEN1 in RCR1
selects the length for every serial word received in the frame. If a dual-phase frame is selected,
RWDLEN1 determines the length of the serial words in phase 1 of the frame, and RWDLEN2 in RCR2
determines the word length in phase 2 of the frame.
8 bits
12 bits
16 bits
20 bits
24 bits
32 bits
Reserved (do not use)
Receive companding mode bits. Companding (COMpress and exPAND) hardware allows compression
and expansion of data in either μ-law or A-law format.
RCOMPAND allows you to choose one of the following companding modes for the McBSP receiver:
For more details about these companding modes, see
Expanding) Data.
No companding, any size data, MSB received first
No companding, 8-bit data, LSB received first
μ-law companding, 8-bit data, MSB received first
A-law companding, 8-bit data, MSB received first
Receive frame-synchronization ignore bit. If a frame-synchronization pulse starts the transfer of a new
frame before the current frame is fully received, this pulse is treated as an unexpected frame-
synchronization pulse. For more details about the frame-synchronization error condition, see
Section 15.5.3, Unexpected Receive Frame-Synchronization Pulse.
Setting RFIG causes the serial port to ignore unexpected frame-synchronization signals during
reception. For more details on the effects of RFIG, see
Frame-Synchronization Ignore Function.
Frame-synchronization detect. An unexpected FSR pulse causes the receiver to discard the contents
of RSR[1,2] in favor of the new incoming data. The receiver:
1. Aborts the current data transfer
2. Sets RSYNCERR in SPCR1
3. Begins the transfer of a new data word
Frame-synchronization ignore. An unexpected FSR pulse is ignored. Reception continues
uninterrupted.
Receive data delay bits. RDATDLY specifies a data delay of 0, 1, or 2 receive clock cycles after frame-
synchronization and before the reception of the first bit of the frame. For more details, see
Section 15.8.12, Set the Receive Data Delay.
0-bit data delay
1-bit data delay
2-bit data delay
Reserved (do not use)
RFRLEN1 RFRLEN2
Not used
0 ≤ RFRLEN2 ≤ 127
Copyright © 2012–2019, Texas Instruments Incorporated
Section 15.1.5, Companding (Compressing and
Section 15.8.10.1, Enable/Disable the Receive
Frame Length
(RFRLEN1 + 1) words
(RFRLEN1 + 1) + (RFRLEN2 + 1) words
(Table 15-78) and XCR2
C28 Multichannel Buffered Serial Port (McBSP)
McBSP Registers
(Table 15-80). These
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