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Functional Description
When the receiver is idle (the UnRx signal is continuously 1), and the data input goes Low (a start bit has
been received), the receive counter begins running and data is sampled on the eighth cycle of Baud16 or
fourth cycle of Baud8 depending on the setting of the HSE bit (bit 5) in UARTCTL, described in
Section
21.3.1.
The start bit is valid and recognized if the UnRx signal is still low on the eighth cycle of Baud16 (HSE
clear) or the fourth cycle of Baud 8 (HSE set), otherwise it is ignored. After a valid start bit is detected,
successive data bits are sampled on every 16th cycle of Baud16 or 8th cycle of Baud8 (that is, one bit
period later) according to the programmed length of the data characters and value of the HSE bit in
UARTCTL. The parity bit is then checked if parity mode is enabled. Data length and parity are defined in
the UARTLCRH register.
Lastly, a valid stop bit is confirmed if the UnRx signal is High, otherwise a framing error has occurred.
When a full word is received, the data is stored in the receive FIFO along with any error bits associated
with that word.
21.3.4 Serial IR (SIR)
The UART peripheral includes an IrDA serial-IR (SIR) encoder/decoder block. The IrDA SIR block
provides functionality that converts between an asynchronous UART data stream and a half-duplex serial
SIR interface. No analog processing is performed on-chip. The role of the SIR block is to provide a digital
encoded output and decoded input to the UART. When enabled, the SIR block uses the UnTx and UnRx
pins for the SIR protocol. These signals should be connected to an infrared transceiver to implement an
IrDA SIR physical layer link. The SIR block can receive and transmit, but it is only half-duplex so it cannot
do both at the same time. Transmission must be stopped before data can be received. The IrDA SIR
physical layer specifies a minimum 10-ms delay between transmission and reception.The SIR block has
two modes of operation:
•
In normal IrDA mode, a zero logic level is transmitted as a high pulse of 3/16th duration of the selected
baud rate bit period on the output pin, while logic one levels are transmitted as a static LOW signal.
These levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the
reception side, the incoming light pulses energize the photo transistor base of the receiver, pulling its
output LOW and driving the UART input pin LOW.
•
In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of
the internally generated IrLPBaud16 signal (1.63 µs, assuming a nominal 1.8432 MHz frequency) by
changing the appropriate bit in the UARTCR register. See the UARTILPR register for more information
on IrDA low-power pulse-duration configuration.
Figure 21-3
shows the UART transmit and receive signals, with and without IrDA modulation.
In both normal and low-power IrDA modes:
•
During transmission, the UART data bit is used as the base for encoding
•
During reception, the decoded bits are transferred to the UART receive logic
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10-ms delay
between transmission and reception. This delay must be generated by software because it is not
automatically supported by the UART. The delay is required because the infrared receiver electronics
might become biased or even saturated from the optical power coupled from the adjacent transmitter LED.
This delay is known as latency or receiver setup time.
1492
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 21-3. IrDA Data Modulation
Start
bit
UnTx
1
0
0
UnTx with IrDA
Bit period
UnRx with IrDA
UnRx
1
0
0
Start
Copyright © 2012–2019, Texas Instruments Incorporated
Data bits
1
0
0
0
1
1
3
Bit period
16
1
0
0
0
1
1
Data bits
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
Stop
bit
1
1
Stop
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