I2C Block Diagram - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Introduction
22.1 Introduction
The M3 Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a
serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial
memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on. The I2C bus may
also be used for system testing and diagnostic purposes in product development and manufacture. The
microcontroller includes two I2C modules, providing the ability to interact (both transmit and receive) with
other I2C devices on the bus.
The two I2C modules include the following features:
• Devices on the I2C bus can be designated as either a master or a slave
– Supports both transmitting and receiving data as either a master or a slave
– Supports simultaneous master and slave operation
• Four I2C modes
– Master transmit
– Master receive
– Slave transmit
– Slave receive
• Two transmission speeds: Standard (100 Kbps) and Fast (400 Kbps)
• Master and slave interrupt generation
– Master generates interrupts when a transmit or receive operation completes (or aborts due to an
error)
– Slave generates interrupts when data has been transferred or requested by a master or when a
START or STOP condition is detected
• Master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode

22.2 I2C Block Diagram

Figure 22-1 shows the block diagram for I2C.
2
I C Control
I2CMSA
I2CMCS
I2CMDR
Interrupt
I2CMTPR
I2CMIMR
I2CMRIS
I2CMMIS
I2CMICR
I2CMCR
22.3 Functional Description
Each I2C module is comprised of both master and slave functions. For proper operation, the SDA and
SCL pins must be configured as open-drain signals. A typical I2C bus configuration is shown in
2.
See Inter-Integrated Circuit (I2C) Interface electricals in the device data manual for I2C timing diagrams.
1522
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-1. I2C Block Diagram
2
I2CSOAR
I C MasterCore
I2CSCSR
I2CSDR
I2CSIMR
I2CSRIS
I2CSMIS
I2CSICR
2
I
Copyright © 2012–2019, Texas Instruments Incorporated
I2CSCL
I2CSDA
I2CSCL
C SlaveCore
I2CSDA
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
I2CSCL
2
I C I/OSelect
I2CSDA
Figure 22-
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