Spi Module Signal Summary; Overview Of Spi Module Registers; Spi Registers - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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12.1.2 SPI Module Signal Summary

Signal Name
External Signals
SPICLK
SPISIMO
SPISOMI
SPISTE
Control
SPI Clock Rate
Interrupt signals
SPIRXINT
SPITXINT

12.1.3 Overview of SPI Module Registers

The SPI port operation is configured and controlled by the registers listed in
Name
SPICCR
SPICTL
SPIST
SPIBRR
SPIEMU
SPIRXBUF
SPITXBUF
SPIDAT
SPIFFTX
SPIFFRX
SPIFFCT
SPIPRI
This SPI has 16-bit transmit and receive capability, with double-buffered transmit and double-buffered
receive. All data registers are 16-bits wide.
The SPI is no longer limited to a maximum transmission rate of LSPCLK/8 in slave mode. The maximum
transmission rate in both slave mode and master mode is now LSPCLK/4.
Writes of transmit data to the serial data register, SPIDAT (and the new transmit buffer, SPITXBUF), must
be left-justified within a 16-bit register.
The control and data bits for general-purpose bit I/O multiplexing have been removed from this peripheral,
along with the associated registers, SPIPC1 (704Dh) and SPIPC2 (704Eh). These bits are now in the
General-Purpose I/O registers.
Twelve registers inside the SPI module control the SPI operations:
• SPICCR (SPI configuration control register). Contains control bits used for SPI configuration
– SPI module software reset
– SPICLK polarity selection
– Four SPI character-length control bits
SPRUHE8E – October 2012 – Revised November 2019
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Table 12-1. SPI Module Signal Summary
Description
SPI clock
SPI slave in, master out
SPI slave out, master in
SPI slave transmit enable
LSPCLK
Transmit interrupt/ Receive Interrupt in non FIFO mode (referred to as SPI INT)
Receive in interrupt in FIFO mode
Transmit interrupt – FIFO
Table 12-2. SPI Registers
Address Range Size (x16)
0x0000-7040
0x0000-7041
0x0000-7042
0x0000-7044
0x0000-7046
0x0000-7047
0x0000-7048
0x0000-7049
0x0000-704A
0x0000-704B
0x0000-704C
0x0000-704F
Copyright © 2012–2019, Texas Instruments Incorporated
Enhanced SPI Module Overview
Table 12-2.
Description
1 SPI Configuration Control Register
1 SPI Operation Control Register
1 SPI Status Register
1 SPI Baud Rate Register
1 SPI Emulation Buffer Register
1 SPI Serial Input Buffer Register
1 SPI Serial Output Buffer Register
1 SPI Serial Data Register
1 SPI FIFO Transmit Register
1 SPI FIFO Receive Register
1 SPI FIFO Control Register
1 SPI Priority Control Register
C28 Serial Peripheral Interface (SPI)
985