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Safety Features
1.6.3 PLLSLIP Detection
On the master subsystem, an interrupt is generated (if enabled) to the NVIC when either the SYSTEM
PLL or the USB PLL goes out of lock when previously locked.
In general, a PLL will go out of lock when the input clock to the PLL fluctuates if there is EMI interference
on the device or if the input clock to PLL goes missing.
NVIC Interrupt No. 89 (System/USB PLL Out-of-Lock) is generated whenever the system PLL or USB PLL
goes out of lock. The interrupt handler should check the status bits to find out which PLL has gone out of
lock. It is the responsibility of the master subsystem application to indicate out-of-lock status to the control
subsystem using an IPC. This has to be taken care of by the user as per the application requirements.
A PLLSLIP will cause a Missing Clock NMI if the REFCLKLO and REFCLKHI registers are configured
exactly to catch the disturbances in the input frequency. However, if a PLLSLIP does not cause a Missing
Clock NMI because the input to PLL is still within the range specified by the REFCLKLO and REFCLKHI
limits, then the PLL will not be bypassed and ePWMs will not trip.
If a user wants to bypass the PLL on a PLLSLIP condition, it is suggested that the user configure the
reference clock limits very strictly as shown in
1.6.4 Control Subsystem PIE Vector Address Validity Check
To handle errors during an interrupt vector fetch, the features below are implemented on the PIE vector
table memory:
•
Two independent memories are reserved for the PIE vector table, one mapped at 0x0D00 and the
other at 0x0E00 in C28 address space. Writes with address 0x0Dxx will get duplicated onto the
memory at 0x0E00, whereas writes to the memory with address 0x0E00 will not get replicated to the
memory at 0x0D00. This enables users to load the vector tables into both memories by just writing to
memory at 0x0D00. Debug is possible during application testing since writes to the memory at 0xE00
are not duplicated in the memory at 0xD00. Dual memories are added mainly to detect more than one
error, which is not possible with just parity. The following is the behavior of accesses to the PIE
memories:
– Data Writes at 0xD00: Writes to both memories
– Data Writes at 0xE00: Writes only to the 0xE00 memory
– Vector Fetch: Fetches from lower RAM at 0xD00 and compares with upper RAM at 0xE00
– Data Read: Can read upper and lower RAM separately
•
On every vector fetch from the PIE, a hardware comparison (no cycle penalty is incurred to do the
comparison) of both vector table outputs is performed and if there is a mismatch between the two
vector table outputs, the PIE returns a vector value that points to a fixed vector. This could be a vector
location in C28 ROM or a fixed RAM or Flash location.
•
Hardware also generates ePWM trip signals which trip the PWM outputs using TRIPIN15
•
If there is no mismatch, the correct vector is jammed on to the C28x CPU program counter.
•
In the event of mismatch, jamming a different vector address onto the C28x CPU program counter
takes care of error handling in such a condition.
The following is the error handling expected to be done by the NMI error handler - configure standby
mode in the C28 LPMCR0 register to enter stand by mode and execute IDLE instruction - C28 subsystem
enters stand by mode.
In the event of a mismatch during a C28 NMI vector fetch, an NMI is generated to the M3 CPU.
124
System Control and Interrupts
Table
1-15.
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
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