Adc Control Register 1 (Adcctl1) (Address Offset 00H); Adc Control Register 1 (Adcctl1) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Analog-to-Digital Converter (ADC)

10.3.11.1 ADC Control Register 1 (ADCCTL1)

NOTE: The following ADC Control Register is EALLOW protected.

Figure 10-17. ADC Control Register 1 (ADCCTL1) (Address Offset 00h)

LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 = always read as 0, write 1 to set; -n = value after reset

Table 10-6. ADC Control Register 1 (ADCCTL1) Field Descriptions

Value Description

Analog Subsystem

ADC module software reset. This bit causes a master reset on the entire ADC module. All register bits

and state machines are reset to the initial state as occurs when the device reset pin is pulled low (or

after a power-on reset). This is a one-time-effect bit, meaning this bit is self-cleared immediately after it

is set to 1. Read of this bit always returns a 0.

Resets the entire ADC module (bit is then set back to 0 by ADC logic)

Note: The ADC module is reset during a system reset. If an ADC module reset is desired at any other

time, you can do so by writing a 1 to this bit.

Note: If the system is reset or the ADC module is reset using Bit 15 (RESET) from the ADC Control

ADC disabled (does not power down ADC)

ADC Enabled. Must set before an ADC conversion (recommend that it be set directly after setting ADC

power-up bits

Set when ADC SOC is generated, cleared per below. Used by the ADC state machine to determine if

ADC is avaliable to sample.

Sequential Mode: Cleared 4 ADC clocks after negative edge of S/H pulse

Simultaneous Mode: Cleared 14 ADC clocks after negative edge of S/H pulse

ADC is available to sample next channel

ADC is busy and cannot sample another channel

SPRUHE8E – October 2012 – Revised November 2019

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