Dac Test (Dactest) Register; Dac Test (Dactest) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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10.4.7.4 DAC Test (DACTEST) Register

15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15-1 Reserved
0 DACTEST
10.5 Analog Subsystem Software
This section describes all of the C/C++ Analog Subsystem functions included in controlSUITE™ and how
to use them.
These functions are used to control the clocking for the Analog Subsystem.
10.5.1 C28 Analog Subsystem Functions
Four functions are defined in the F28M35x_GlobalPrototypes.h file:
• unsigned short InitAnalogSystemClock (unsigned short ClockDivider)
• unsigned short AnalogClockEnable (unsigned short AnalogConfigReg, unsigned short
AnalogClockMask)
• unsigned short AnalogClockDisable (unsigned short AnalogConfigReg, unsigned short
AnalogClockMask)
• unsigned short ReadAnalogClockStatus (unsigned short AnalogConfigReg)
There are also #define values defined in the F28M35x_AnalogSysCtrl_defines.h file which can be passed
into the functions above.
10.5.1.1 InitAnalogSystemClock Function
The InitAnalogSystemClock function should be the first function called if the Analog Subsystem is to be
used. This function allows configuration of the Analog Subsystem clock divider and checks if the Analog
Common Interface Bus (ACIB) clock is enabled. The Analog Subsystem is clocked off of PLLSYSCLK.
Valid #define values for the ClockDivider parameter are located in the F28M35x_AnalogSysCtrl_defines.h
file and listed below.
#define ACLKDIVOFF
#define ACLKDIV1
#define ACLKDIV2
#define ACLKDIV4
#define ACLKDIV8
NOTE: The maximum clock frequency for the Analog Subsystem clock is 37.5 MHz.
This function is successful if it returns a value of 0xA005.
SPRUHE8E – October 2012 – Revised November 2019
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Figure 10-58. DAC Test (DACTEST) Register
Reserved
R-0
Table 10-40. DAC Test (DACTEST) Register Field Descriptions
Value Description
Reserved
DAC test
0 DAC 3 is not connected to ADC1 or DAC6 is not connected to ADC2
1 DAC 3 is connected to ADC1 or DAC6 is connected to ADC2
Note: These bits are purely for test purposes only. Do not use COMP3 or COMP6 while these bits
are set.
0 // Clock divider off
1 // Clock divider /1 (PLLSYSCLK/1)
2 // Clock divider /2 (PLLSYSCLK/2)
3 // Clock divider /4 (PLLSYSCLK/4)
4 // Clock divider /8 (PLLSYSCLK/8)
Copyright © 2012–2019, Texas Instruments Incorporated
Analog Subsystem Software
1 0
DACTEST
R/W-0
943
Analog Subsystem