Ethernet Phy Management Register 0 - Control (Mr0) Register; Ethernet Phy Management Register 0 - Control (Mr0) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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19.7 MII Management Register Descriptions
The IEEE 802.3 standard specifies a register set for controlling and gathering status from the PHY layer.
The registers are collectively known as the MII Management registers. The
access the MII Management registers. All addresses given are absolute. Addresses not listed are
reserved; these addresses should not be written to and any data read should be ignored. Also see
Table 19-2.
PHY registers MR0 – MR6 are not located on the microcontroller. These registers are located on IEEE
802.3 compliant Ethernet external PHYs. These registers are defined for software ease of use. See
registers MACMCTL, MACMTXD, and MACMRXD for instructions on how to read and write to the
registers on an external Ethernet PHY.
19.7.1 Ethernet PHY Management Register 0 – Control (MR0) Register, address 0x00
This register enables software to configure the operation of an external PHY. The default settings of these
registers are designed to initialize the Ethernet external PHY to a normal operational mode without
configuration
Figure 19-21. Ethernet PHY Management Register 0 – Control (MR0) Register
15 14
RESET LOOPBK
R/W-0 R/W-0
7 6
COLT
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19-20. Ethernet PHY Management Register 0 – Control (MR0) Register Field Descriptions
Bit Field
15 RESET
14 LOOPBK
13 SPEEDSL
12 ANEGEN
11 PWRDN
10 ISO
SPRUHE8E – October 2012 – Revised November 2019
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13 12
SPEEDSL ANEGEN
R/W-0 R/W-0
Value Description
Reset Registers
0 No effect
1 The PHY layer registers reset to their default state and the internal state machines are reinitialized
Once the reset operation has completed, this bit is automatically cleared by hardware.
Loopback Mode
0 No effect
1 Enables the Loopback mode of operation. The receiver ignores external inputs and receives the
data that is transmitted by the transmitter.
Speed Select
0 Enables the 10 Mbps mode of operation (10BASE-T).
1 Enables the 100 Mbps mode of operation (100BASE-TX).
Auto-Negotiation Enable
0 No effect
1 Enables the auto-negotiation process.
Power down
0 No effect
1 The PHY layer is configured to be in a low-power consuming state. All data on the data inputs is
ignored.
Isolate
0 No effect
1 The transmit and receive data paths are isolated and all data being transmitted and received is
ignored.
Copyright © 2012–2019, Texas Instruments Incorporated
MII Management Register Descriptions
Section 19.6.9
11 10
PWRDN ISO
R/W-0 R/W-0
Reserved
R-0
M3 Ethernet Media Access Controller (EMAC)
is used to
9 8
RANEG DUPLEX
R/W-0 R/W-0
0
1439