Master Subsystem Ipc Registers; M3 To C28 Ipc Set (Mtocipcset) Register; Μcrcres Register Field Descriptions; M3 To C28 Ipc Set (Mtocipcset) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Bit Field
31-0 RESULT

1.13.11 Master Subsystem IPC Registers

The below registers are mapped to the master subsystem address map only.

1.13.11.1 M3 to C28 IPC Set (MTOCIPCSET) Register

31 30
IPC32 IPC31
W-0 W-0
23 22
IPC24 IPC23
W-0 W-0
15 14
IPC16 IPC15
W-0 W-0
7 6
IPC8 IPC7
W-0 W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31 IPC32
30 IPC31
29 IPC30
28 IPC29
27 IPC28
26 IPC27
25 IPC26
24 IPC25
23 IPC24
SPRUHE8E – October 2012 – Revised November 2019
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Table 1-175. µCRCRES Register Field Descriptions
Value Description
This register contains the calculated CRC. This gets updated for every read (byte access) to
mirrored address locations.
Figure 1-164. M3 to C28 IPC Set (MTOCIPCSET) Register
29 28
IPC30 IPC29
W-0 W-0
21 20
IPC22 IPC21
W-0 W-0
13 12
IPC14 IPC13
W-0 W-0
5 4
IPC6 IPC5
W-0 W-0
Table 1-176. M3 to C28 IPC Set (MTOCIPCSET) Field Descriptions
Value Description
0 MTOCIPCSET Flag 32. M3 to C28 core IPC flag 32 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 31. M3 to C28 core IPC flag 31 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 30. M3 to C28 core IPC flag 30 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 29. M3 to C28 core IPC flag 29 set. If a bit is set by writing a ''1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 28. M3 to C28 core IPC flag 28 set. If a bit is set by writing a ''1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 27. M3 to C28 core IPC flag 27 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 26. M3 to C28 core IPC flag 26 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 25. M3 to C28 core IPC flag 25 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
0 MTOCIPCSET Flag 24. M3 to C28 core IPC flag 24 set. If a bit is set by writing a '1' then the
corresponding bit in MTOCIPCFLG is set. The status of this bit is not readable in this register – it is
readable in the MTOCIPCFLG and STS registers.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
IPC28 IPC27
W-0 W-0
19 18
IPC20 IPC19
W-0 W-0
11 10
IPC12 IPC11
W-0 W-0
3 2
IPC4 IPC3
W-0 W-0
System Control and Interrupts
System Control Registers
25 24
IPC26 IPC25
W-0 W-0
17 16
IPC18 IPC17
W-0 W-0
9 8
IPC10 IPC9
W-0 W-0
1 0
IPC2 IPC1
W-0 W-0
277