Master Access Violation Flag Register (Cmavflg); Master Access Violation Force Register (Cmavfrc); Master Access Violation Flag Register (Cmavflg) Field Descriptions; Master Access Violation Force Register (Cmavfrc) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

RAM Control Module Registers

5.2.4.17 Master Access Violation Flag Register (CMAVFLG)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-81. Master Access Violation Flag Register (CMAVFLG) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
1 DMAWRITE
0 CPUFETCH

5.2.4.18 Master Access Violation Force Register (CMAVFRC)

31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-82. Master Access Violation Force Register (CMAVFRC) Field Descriptions
Bit Field
31-3 Reserved
2 CPUWRITE
530
Internal Memory
Figure 5-72. Master Access Violation Flag Register (CMAVFLG)
Reserved
R-0
Value Description
Reserved
Master CPU Write Access Violation Flag
0 Master CPU write access violation did not occur.
1 Master CPU write access violation has occurred. The C28x CPU tried to write into a RAM Block for
which CPUWRPROT is set to 1.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Master DMA Write Access Violation Flag
0 Master DMA write access violation did not occur.
1 Master DMA write access violation has occurred. The C28x µDMA tried to write into a RAM Block
for which DMAWRPROT is set to 1. In this case, writes are ignored.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Master CPU Fetch Access Violation Flag
0 Master CPU fetch access violation did not occur.
1 Master CPU fetch access violation has occurred. The C28x CPU tried to fetch code from a RAM
Block for which FETCHPROT is set to 1.
Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR
register.
Figure 5-73. Master Access Violation Force Register (CMAVFRC)
Reserved
R-0
Value Description
Reserved
Master CPU Write Access Violation Force. Any reads to this bit will return a 0.
0 No effect.
1 Sets the CPUFETCH flag in the CNMAVFLG register.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0
3 2
CPUWRITE
R-0
Reserved
R-0
3 2
CPUWRITE
R/W=1-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
16
1 0
DMAWRITE CPUFETCH
R-0 R-0
16
1 0
DMAWRITE CPUFETCH
R/W=1-0 R/W=1-0
Submit Documentation Feedback