Gptm Timer B Prescale Match (Gptmtbpmr) Register; Gptm Timer A (Gptmtar) Register; Gptm Timer B Prescale Match (Gptmtbpmr) Register Field Descriptions; Gptm Timer A (Gptmtar) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
Figure 2-21. GPTM Timer B Prescale Match (GPTMTBPMR) Register
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-20. GPTM Timer B Prescale Match (GPTMTBPMR) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 TBPSMR
2.6.17 GPTM Timer A (GPTMTAR) Register, offset 0x048
The GPTM Timer A (GPTMTAR) register shows the current value of the Timer A counter in all cases
except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the
number of edges that have occurred. In the Input Edge Time mode, this register contains the time at
which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits
of the count.
When a GPTM is configured to one of the 32-bit modes, GPTMTAR appears as a 32-bit register (the
upper 16-bits correspond to the contents of the GPTM Timer B (GPTMTBR) register). In the16-bit Input
Edge Count, Input Edge Time, and PWM modes, bits 15:0 contain the value of the counter and bits 23:16
contain the value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 always read as 0. To
read the value of the prescaler in 16-bit One-Shot and Periodic modes, read bits [23:16] in the GPTMTAV
register.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-21. GPTM Timer A (GPTMTAR) Register Field Descriptions
Bit Field
31-0 TAR 0xFFFF
2.6.18 GPTM Timer B (GPTMTBR) Register, offset 0x04C
The GPTM Timer B (GPTMTBR) register shows the current value of the Timer B counter in all cases
except for Input Edge Count and Time modes. In the Input Edge Count mode, this register contains the
number of edges that have occurred. In the Input Edge Time mode, this register contains the time at
which the last edge event took place. Also in Input Edge-Count mode, bits 23:16 contain the upper 8 bits
of the count.
When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are
loaded into the upper 16 bits of the GPTMTAR register. Reads from this register return the current value
of Timer B. In a 16-bit mode, bits 15:0 contain the value of the counter and bits 23:16 contain the value of
the prescaler in Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the
count. Bits 31:24 are reserved in both cases.
328
M3 General-Purpose Timers
Reserved
R-0
Value Description
Reserved
0x00 GPTM Timer B Prescale Match
This value is used alongside GPTMTBMATCHR to detect timer match events while using a
prescaler.
Figure 2-22. GPTM Timer A (GPTMTAR) Register
Value Description
GPTM TimerA Register
.FFFF
A read returns the current value of the GPTM Timer A Count Register, in all cases except for Input
Edge Count and Time modes. In the Input Edge Count mode, this register contains the number of
edges that have occurred. In the Input Edge Time mode, this register contains the time at which the
last edge event took place.
Copyright © 2012–2019, Texas Instruments Incorporated
TAR
R-1
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
8 7
TBPSMR
R/W-0
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