Flash Bank Pump Control Register 2 (Fpac2); Flash Module Access Control Register (Fmac); Flash Read Interface Control Register (Frd_Intf_Ctrl); Flash Bank Pump Control Register 2 (Fpac2) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Flash Registers
Table 5-126. Flash Bank Pump Control Register 1 (FPAC1) Field Descriptions (continued)
Bit Field
0 PMPPWR
5.4.3.7

Flash Bank Pump Control Register 2 (FPAC2)

31
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-127. Flash Bank Pump Control Register 2 (FPAC2) Field Descriptions
Bit Field
31-16 Reserved
15-0 PAGP
5.4.3.8

Flash Module Access Control Register (FMAC)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-128. Flash Module Access Control Register (FMAC) Field Descriptions
Bit Field
31-3 Reserved
2-0 BANK
5.4.3.9

Flash Read Interface Control Register (FRD_INTF_CTRL)

Figure 5-121. Flash Read Interface Control Register (FRD_INTF_CTRL)
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
570
Internal Memory
Value Description
Flash Charge Pump Fallback Power Mode. This bit selects what power mode the charge pump
enters after the pump active grace period (PAGP) counter has timed out.
0 Sleep (all pump circuits disabled)
1 Active (all pump circuits active)
Note: As the pump is shared between both M3 and C28x banks, if an access is made either to the
M3 bank or C28x bank, the value of this bit changes to 1 (active).
Figure 5-119. Flash Bank Pump Control Register 2 (FPAC2)
R-0
Value Description
Reserved
Pump Active Grace Period. This register contains the starting count value for the PAGP mode down
counter. Any access to flash memory causes the counter to reload with the PAGP value. After the
last access to flash memory, the down counter delays from 0 to 65535 prescaled C28x SYSCLK
clock cycles before entering one of the charge pump fallback power modes as determined by
PUMPPWR in the FPAC1 register.
Note: The PAGP down counter is clocked by the same prescaled clock as the BAGP down counter
which is divided by 16 of input C28x SYSCLK.
Figure 5-120. Flash Module Access Control Register (FMAC)
Reserved
R-0
Value Description
Reserved
Bank ID. Controls the bank on which the Flash FSM operations will be performed. For these
devices, the value of this field will be 0 as there is only one bank in the control subsystem
Reserved
R-0
Copyright © 2012–2019, Texas Instruments Incorporated
16 15
2 1
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SPRUHE8E – October 2012 – Revised November 2019
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PAGP
R/W-0
3 2
BANK
0
PROG_CACHE_EN
R/W-0 R/W-0
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0
0
R-0