Table of Contents
Advertisement
www.ti.com
15.3.4 Implementing the AC97 Standard With a Dual-Phase Frame
Figure 15-11
shows an example of the Audio Codec '97 (AC97) standard, which uses the dual-phase
frame feature. Notice that words, not individual bits, are shown on the D(R/X) signal. The first phase (P1)
consists of a single 16-bit word. The second phase (P2) consists of twelve 20-bit words. The phase
configurations are listed after the figure.
Figure 15-11. Implementing the AC97 Standard With a Dual-Phase Frame
P1W1
FS(R/X)
D(R/X)
•
(R/X)PHASE = 1: Dual-phase frame
•
(R/X)FRLEN1 = 0000000b: 1 word in phase 1
•
(R/X)WDLEN1 = 010b: 16 bits per word in phase 1
•
(R/X)FRLEN2 = 0001011b: 12 words in phase 2
•
(R/X)WDLEN2 = 011b: 20 bits per word in phase 2
•
CLKRP/CLKXP= 0: Receive data sampled on falling edge of internal CLKR / transmit data clocked on
rising edge of internal CLKX
•
FSRP/FSXP = 0: Active-high frame-sync signal
•
(R/X)DATDLY = 01b: Data delay of 1 clock cycle (1-bit data delay)
Figure 15-12
shows the timing of an AC97-standard data transfer near frame synchronization. In this
figure, individual bits are shown on D(R/X). Specifically, the figure shows the last two bits of phase 2 of
one frame and the first four bits of phase 1 of the next frame. Regardless of the data delay, data transfers
can occur without gaps. The first bit of the second frame (P1W1B15) immediately follows the last bit of the
first frame (P2W12B0). Because a 1-bit data delay has been chosen, the transition on the frame-sync
signal can occur when P2W12B0 is transferred.
Figure 15-12. Timing of an AC97-Standard Data Transfer Near Frame Synchronization
MCLKRA
MFSRA
P2W12B1
MDRA
15.3.5 McBSP Reception
This section explains the fundamental process of reception in the McBSP. For details about how to
program the McBSP receiver, see Receiver Configuration in
Figure 15-13
and
Figure 15-14
physical path for the data.
reception scenario. A description of the process follows the figures.
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
P2W1
P2W2
P2W3
P2W4
1-bit data delay
16 bits
20 bits
PxWy = Phase x Word y
1-bit data delay
P2W12B0
P1W1B15
PxWyBz = Phase x Word y Bit z
show how reception occurs in the McBSP.
Figure 15-14
is a timing diagram showing signal activity for one possible
Copyright © 2012–2019, Texas Instruments Incorporated
P2W5
P2W6
P2W7
P2W8
P2W9
P1W1B14
P1W1B13
Section
15.8.
C28 Multichannel Buffered Serial Port (McBSP)
Frame Phases
P2W10
P2W11
P2W12
P1W1B12
Figure 15-13
shows the
1083
Advertisement
Chapters
Table of Contents
