Peripheral Clock Control Register 1 (Pclkcr1); Peripheral Clock Control Register 0 (Pclkcr0) Register Field Descriptions; Peripheral Clock Control Register 1 (Pclkcr1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

System Control Registers
Table 1-136. Peripheral Clock Control Register 0 (PCLKCR0) Register Field Descriptions
Bit Field
15-3 Reserved
12 MENCLK
11 Reserved
10 SCIAENCLK
9 Reserved
8 SPIAENCLK
7-5 Reserved
4 I2CENCLK
3 Reserved
2 TBCLKSYNC
1 Reserved
0 HRPWMENCLK

1.13.7.31 Peripheral Clock Control Register 1 (PCLKCR1)

15 14
EQEP2ENCLK EQEP1ENCLK
R/W-0 R/W-0
7 6
EPWM8ENCLK EPWM7ENCLK EPWM6ENCLK EPWM5ENCLK EPWM4ENCLK EPWM3ENCLK EPWM2ENCLK EPWM1ENCLK
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-137. Peripheral Clock Control Register 1 (PCLKCR1) Register Field Descriptions
Bit Field
15-14 EQEPxENCLK
(n = 2-1)
13-8 ECAPxENCLK
(n = 6-1)
250
System Control and Interrupts
Value Description
Reserved
McBSP-A Clock Enable
When set, this enables the clock to the McBSP-A module.
0 McBSP-A clock is disabled
1 McBSP-A clock is enabled
Reserved
SCI-A Clock Enable
When set, this enables the clock to the C28 SCI-A module.
0 SCI-A clock is disabled
1 SCI-A clock is enabled
Reserved
SPI-A Clock EnableWhen set, this enables the clock to the C28 SPI-A module.
0 SPI-A clock is disabled
1 SPI-A clock is enabled
Reserved
I2C-A Clock Enable
When set, this enables the clock to the C28 I2C-A module.
0 I2C-A clock is disabled
1 I2C-A clock is enabled
Reserved
ePWM Clock Sync
When set PWM time bases of all modules start counting.
Reserved
HRPWM Clock Enable
When set, this enables the clock to the HRPWM module.
0 HRPWM clock is disabled
1 HRPWM clock is enabled
Figure 1-126. Peripheral Clock Control Register 1 (PCLKCR1)
13 12
ECAP6ENCLK ECAP5ENCLK
R/W-0 R/W-0
5 4
R/W-0 R/W-0
Value Description
eQEP2-1 Clock Enables
When set, this enables the clock to the respective eQEP module.
0 Clock is disabled
1 Clock is enabled
eCAP6-1 Clock Enables
When set, this enables the clock to the respective eCAP module.
0 Clock is disabled
1 Clock is enabled
Copyright © 2012–2019, Texas Instruments Incorporated
11 10
ECAP4ENCLK ECAP3ENCLK
R/W-0 R/W-0
3 2
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
9 8
ECAP2ENCLK ECAP1ENCLK
R/W-0 R/W-0
1 0
R/W-0 R/W-0
Submit Documentation Feedback