Texas Instruments TMS570LS0 32 Series Manual
Texas Instruments TMS570LS0 32 Series Manual

Texas Instruments TMS570LS0 32 Series Manual

6- and 32-bit risc flash microcontroller
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TMS570LS0x32 16- and 32-Bit RISC Flash Microcontroller

1 Device Overview

1.1

Features

1
• High-Performance Automotive-Grade
Microcontroller for Safety-Critical Applications
– Dual CPUs Running in Lockstep
– ECC on Flash and RAM Interfaces
– Built-In Self-Test for CPU and On-Chip RAMs
– Error Signaling Module With Error Pin
– Voltage and Clock Monitoring
®
®
• ARM
Cortex
-R4 32-Bit RISC CPU
– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline
– 8-Region Memory Protection Unit (MPU)
– Open Architecture With Third-Party Support
• Operating Conditions
– 80-MHz System Clock
– Core Supply Voltage (V
– I/O Supply Voltage (V
– ADC Supply Voltage (V
• Integrated Memory
– Up to 384KB of Program Flash With ECC
– 32KB of RAM With ECC
– 16KB of Flash for Emulated EEPROM With
ECC
• Hercules™ Common Platform Architecture
– Consistent Memory Map Across Family
– Real-Time Interrupt (RTI) Timer (OS Timer)
– 96-Channel Vectored Interrupt Module (VIM)
– 2-Channel Cyclic Redundancy Checker (CRC)
• Frequency-Modulated Phase-Locked Loop
(FMPLL) With Built-In Slip Detector
• IEEE 1149.1 JTAG Boundary Scan and ARM
CoreSight™ Components
• Advanced JTAG Security Module (AJSM)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
): 1.2-V Nominal
CC
): 3.3-V Nominal
CCIO
): 3.3-V Nominal
CCAD
Tools &
Technical
Software
Documents
SPNS186B – OCTOBER 2012 – REVISED JUNE 2015
• Multiple Communication Interfaces
– Two CAN Controllers (DCANs)
DCAN1 - 32 Mailboxes With Parity
Protection
DCAN2 - 16 Mailboxes With Parity
Protection
Compliant to CAN Protocol Version 2.0B
– Multibuffered Serial Peripheral Interface
(MibSPI) Module
128 Words With Parity Protection
– Two Standard Serial Peripheral Interface (SPI)
Modules
– UART (SCI) Interface With Local Interconnect
Network (LIN 2.1) Interface Support
• Next Generation High-End Timer (N2HET) Module
– Up to 19 Programmable Pins
– 128-Word Instruction RAM With Parity
Protection
– Includes Hardware Angle Generator
– Dedicated High-End Timer Transfer Unit (HTU)
With MPU
• Enhanced Quadrature Encoder Pulse (eQEP)
Module
– Motor Position Encoder Interface
• 12-Bit Multibuffered Analog-to-Digital Converter
(ADC) Module
– 16 Channels
– 64 Result Buffers With Parity Protection
• Up to 45 General-Purpose Input/Output (GPIO)
Pins
– 8 Dedicated Interrupt-Capable GPIO Pins
• Package
– 100-Pin Quad Flatpack (PZ) [Green]
Support &
Community
TMS570LS0432, TMS570LS0332

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Summary of Contents for Texas Instruments TMS570LS0 32 Series

  • Page 1: Device Overview

    Sample & Support & Product Tools & Technical Community Folder Software Documents TMS570LS0432, TMS570LS0332 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 TMS570LS0x32 16- and 32-Bit RISC Flash Microcontroller 1 Device Overview Features • High-Performance Automotive-Grade • Multiple Communication Interfaces Microcontroller for Safety-Critical Applications –...
  • Page 2: Applications

    Active Driver Assistance Systems • Electric Power Steering (EPS) • Aerospace and Avionics • Electric Pump Control • Railway Communications • Battery-Management Systems • Off-road Vehicles Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 3: Description

    ECLK pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as an indicator of the device operating frequency. Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 4 14.00 mm × 14.00 mm TMS570LS0332PZ LQFP (100) 14.00 mm × 14.00 mm (1) For more information, see Section 9, Mechanical Packaging and Orderable Information. Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 5: Functional Block Diagram

    VCCAD / ADREFHI with Parity with Parity VSSAD / ADREFLO eQEP IOMM The TMS570LS0332 device only supports 256KB Flash with ECC. Figure 1-1. Functional Block Diagram Device Overview Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 6: Table Of Contents

    ..............Clock Monitoring 8.10 Module Certifications ......... Mechanical Packaging and Orderable Glitch Filters ................Addendum Device Memory Map ......Packaging Information Table of Contents Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 7: Revision History

    (Device Identification Code Register): Added silicon revision B device identification code • Section 8.9 (Die Identification Registers): Updated/Changed the DIEIDL and DIEIDH to point to the original ................ registers at location 0xFFFFFF7C and 0xFFFFFF80 Revision History Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 8: Device Comparison

    (3) Superset device (4) Total number of pins that can be used as general-purpose input or output when not used as part of a peripheral. Device Comparison Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 9: Terminal Configuration And Functions

    Figure 4-1. PZ QFP Package Pinout (100-Pin) Note: Pins can have multiplexed functions. Only the default function is depicted in Figure 4-1. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 10: Terminal Functions

    N2HET[6] N2HET[8] N2HET[10] N2HET[12] N2HET[14] N2HET[16] MIBSPI1nCS[1]/EQEPS/ N2HET[17] N2HET[18] MIBSPI1nCS[2]/N2HET[20]/ N2HET[19] MIBSPI1nCS[2]/N2HET[20]/ N2HET[19] N2HET[22] N2HET[24] MIBSPI1nCS[3]/N2HET[26] ADEVT/N2HET[28] GIOA[7]/N2HET[29] MIBSPI1nENA/N2HET[23]/ N2HET[30] GIOA[6]/SPI2nCS[1]/N2HET[31] Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 11 CAN1 Receive, or general-purpose I/O (GPIO) 20 µA CAN1TX CAN1 Transmit, or GPIO CAN2RX CAN2 Receive, or GPIO CAN2TX CAN2 Transmit, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 12 PULL TYPE DESCRIPTION TYPE PULL SIGNAL NAME STATE LINRX Pullup Programmable, LIN Receive, or GPIO 20 µA LINTX LIN Transmit, or GPIO Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 13 TI recommends that an external pullup resistor is connected to this terminal. This terminal has a glitch filter. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 14 None Flash external pump voltage (3.3 V). This Power terminal is required for both flash read and flash program and erase operations. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 15 SIGNAL NAME STATE Ground None Device Ground Reference. This is a single ground reference for all supplies except for the ADC supply. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 16: Output Multiplexing And Control

    The pin is connected as input to both the GPIO and N2HET modules. That is, there is no input multiplexing on this pin. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 17: Special Multiplexed Options

    N2HET PIN_nDISABLE input of the N2HET module. • PINMMR9[0] = 0 and PINMMR9[1] = 0 is an illegal combination and behavior defaults to PINMMR9[0] = 1. Terminal Configuration and Functions Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 18: Specifications

    (2) To avoid significant degradation, the device power-on hours (POH) must be limited to those specified in this table. To convert to equivalent POH for a specific temperature profile, see the Calculating Equivalent Power-on-Hours for Hercules Safety MCUs Application Report (SPNA207). Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 19: Recommended Operating Conditions

    VCLK - Primary peripheral clock frequency VCLK VCLK2 - Secondary peripheral clock frequency VCLK2 VCLKA1 - Primary asynchronous peripheral clock VCLKA1 frequency RTICLK - clock frequency RTICLK VCLK Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 20: Wait States Required

    The flash wrapper defaults to nonpipelined mode with address wait states disabled, ASWSTEN=0; the main memory random-read data wait state, RWAIT=1; and the emulation memory random-read wait states, EWAIT=1. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 21: Power Consumption

    (3) LBIST and PBIST currents are for a short duration, typically less than 10 ms. They are usually ignored for thermal calculations for the device and the voltage regulator (4) Maximum current requirement of the three combined supplies Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 22: Thermal Resistance Characteristics For Pz

    (1) Source currents (out of the device) are negative while sink currents (into the device) are positive. (2) This does not apply to the nPORRST pin. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 23: Output Buffer Drive Strengths

    (1) Either SPI2PC9[11] or SPI2PC9[24] can change the output strength of the SPI2SOMI pin. In case of a 32-bit write where these 2 bits differ, SPI2PC9[11] determines the drive strength. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 24: Input Timings

    = peripheral VBUS clock cycle time = 1 / f c(VCLK) (VCLK) (2) The timing shown in Figure 5-2 is only valid for pin used in GIO mode. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 25: Output Timings

    CL = 150 pF 2-mA-z mode CL = 15 pF CL = 50 pF Fall time, t CL = 100 pF CL = 150 pF Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 26 (1) This specification does not account for any output buffer drive strength differences or any external capacitive loading differences. Check Table 5-3 for output buffer drive strength information on each signal. Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 27: System Information And Electrical Specifications

    UNIT Width of glitch on VCC that can be filtered 1000 Width of glitch on VCCIO that can be filtered 1000 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 28: Power Sequencing And Power-On Reset

    3497 oscillator cycles The CPU reset is released at the end of this sequence and fetches the first instruction from address 0x00000000. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 29 NOTE: There is no timing dependency between the ramp of the VCCIO and the VCC supply voltage; this is just an exemplary drawing. Figure 6-1. nPORRST Timing Diagram System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 30: Warm Reset (Nrst)

    Pulses less than MIN will be filtered out, pulses greater than MAX will 2000 f(nRST) generate a reset (1) Assumes the oscillator has started up and stabilized before nPORRST is released. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 31: Arm Cortex-R4 Cpu Information

    Different orientation; for example, CPU1 = "north" orientation, CPU2 = "flip west" orientation • Dedicated guard ring for each CPU Flip West North Figure 6-2. Dual - CPU Orientation System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 32 Complete isolation of the self-tested CPU core from the rest of the system during the self-test run • Ability to capture the failure interval number • Timeout counter for the CPU self-test run as a fail-safe feature System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 33 19110 87.67 20475 88.11 21840 88.53 23205 88.93 24570 89.26 25935 89.56 27300 89.86 28665 90.1 30030 90.36 31395 90.62 32760 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 34 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 www.ti.com Table 6-7. CPU Self-Test Coverage (continued) INTERVALS TEST COVERAGE, % TEST CYCLES 90.86 34125 91.06 35490 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 35: Clocks

    Note A: The values of C1 and C2 should be provided by the resonator/crystal vendor. Note B: Kelvin_GND should not be connected to any other GND. Figure 6-4. Recommended Crystal/Clock Connection System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 36 Provides a comparison clock for the crystal oscillator failure detection circuit. BIAS_EN CLK80K LFEN LF_TRIM Low-Power HFEN CLK10M Oscillator HF_TRIM CLK10M_VALID nPORRST Figure 6-5. LPO Block Diagram System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 37 PLL1 Reference Clock frequency INTCLK Post-ODCLK – PLL1 Post-divider input clock frequency post_ODCLK VCOCLK – PLL1 Output Divider (OD) input clock frequency VCOCLK System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 38 Application can ensure this by programming the RTI1DIV field of the RCLKSRC register, if necessary • Is disabled through the CDDISx registers bit 6 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 39 Baud Rate Phase_seg1 Loop High SPIx,MibSPIx MibADC External Clock Resolution Clock CAN Baud Rate N2HET DCAN1, 2 Figure 6-7. Device Clock Domains System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 40 1101 Reserved 1101 Oscillator Valid status 1110 Reserved 1110 Oscillator Valid status 1111 Flash HD Pump Oscillator 1111 Oscillator Valid status System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 41: Clock Monitoring

    Table 6-14. DCC Counter 0 Clock Sources TEST MODE CLOCK SOURCE [3:0] CLOCK NAME Others Oscillator (OSCIN) High-frequency LPO Test clock (TCK) VCLK System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 42 Main PLL free-running clock output Low-frequency LPO High-frequency LPO Flash HD pump oscillator EXTCLKIN Ring oscillator 0x8 - 0xF VCLK HCLK System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 43: Glitch Filters

    (1) The glitch filter design on the nPORRST signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, I/O pins, and so forth) without also generating a valid reset signal to the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 44: Device Memory Map

    RESERVED 0x08407FFF RAM - ECC 0x08400000 RESERVED 0x08007FFF RAM (32KB) 0x08000000 RESERVED 0x0005FFFF Flash (384KB) 0x00000000 Figure 6-9. TMS570LS0432 Memory Map System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 45 The Flash memory in all configurations is mirrored to support ECC logic testing. The base address of the mirrored Flash image is 0x2000 0000. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 46 Wrap around for accesses between Table offsets 0x180 and 0x3FFF. Aborts generated for accesses beyond 0x4000 (1) The TMS570LS0332 device has only 256KB of flash. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 47 PPS1 0xFFFF_E600 0xFFFF_E6FF 256B 256B effect IOMM Generates address error interrupt if Multiplexing PPS2 0xFFFF_EA00 0xFFFF_EBFF 512B 512B enabled. control module System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 48 System Module - Reads return zeros, writes have no Frame 1 (see PPS7 0xFFFF_FF00 0xFFFF_FFFF 256B 256B effect device TRM) System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 49 OTP, ECC, EEPROM and CPU Data RAM System Module Bank Control Registers And Memories CPU READ User/Privilege CPU WRITE User/Privilege Privilege System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 50: Flash Memory

    (3) Flash bank7 is an FLEE bank and can be programmed while executing code from flash bank0. It is 72-bit wide with ECC support. (4) Code execution is not allowed from flash bank7. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 51 MCR p15, #0, r1, c1, c0, #1 6.9.4 Flash Access Speeds For information on flash memory access speeds and the relevant wait states required, see Section 5.6. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 52: Flash Program And Erase Timings For Program Flash

    (2) During bank erase, the selected sectors are erased simultaneously. The time to erase the bank is specified as equal to the time to erase a sector. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 53: Tightly Coupled Ram Interface Module

    Error Signaling Module. The module also captures the peripheral RAM address that caused the parity error. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 54: On-Chip Sram Initialization And Testing

    The PBIST ROM clock can be divided down from HCLK. The divider is selected by programming the ROM_DIV field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 55 SPI Global Control Register 0 (SPIGCR0). This is independent of whether the application chooses to initialize the MibSPI1 RAMs using the system module auto-initialization method. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 56: Vectored Interrupt Manager

    ESM Low level interrupt SYSTEM Software interrupt (SSI) PMU interrupt GIO interrupt B N2HET N2HET level 1 interrupt HTU level 1 interrupt System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 57 Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR entry; therefore only request channels 0..94 can be used and are offset by 1 address in the VIM RAM. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 58: Real-Time Interrupt Module

    RTICAFRCx RTICAUCx CAP event source 0 External control CAP event source 1 Figure 6-12. Counter Block Diagram System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 59: Error Signaling Module

    The device response to each error is determined by the severity group it is connected to. Table 6-26 shows the channel assignment for each group. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 60 FMC - correctable error (EEPROM bank access) Group1 FMC - uncorrectable error (EEPROM bank access) Group1 IOMM - Mux configuration error Group1 Reserved Group1 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 61 RAM odd bank (B1TCM) - address bus parity error Group2 Reserved Group2 Reserved Group2 Reserved Group2 TCM - ECC live lock detect Group2 Reserved Group2 Reserved Group2 Reserved Group2 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 62 Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 Reserved Group3 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 63: Reset / Abort / Error Sources

    (1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage of the CPU. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 64: Digital Windowed Watchdog

    The watchdog is disabled by default and must be enabled by the application. Once enabled, the watchdog can only be disabled upon a system reset. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 65: Debug Subsystem

    The JTAG ID code for this device is the same as the device ICEPick Identification Code. Table 6-29. JTAG Identification Code SILICON REVISION IDENTIFICATION CODE Initial Silicon 0x0B97102F Revision A 0x1B97102F Revision B 0x2B97102F System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 66 Pointer to Cortex-R4 0x0000 1003 0x001 Reserved 0x0000 2002 0x002 Reserved 0x0000 3002 0x003 Reserved 0x0000 4002 0x004 End of table 0x0000 0000 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 67 -TDO) (1) Timings for TDO are specified for a maximum of 50 pF load on TDO RTCK Figure 6-15. JTAG Timing System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 68 A secure device only permits JTAG accesses to the AJSM scan chain through the Secondary Tap # 2 of the ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in this state. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 69 Figure 6-17. Boundary Scan Implementation (Conceptual Diagram) Data is serially shifted into all boundary-scan buffers through TDI, and out through TDO. System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 70: Peripheral Information And Electrical Specifications

    Embedded calibration logic • Enhanced power-down mode – Optional feature to automatically power down ADC core when no conversion is in progress Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 71 RTI module. That is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the CPU. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 72 = 10 in 10-bit mode and 12 in 12-bit mode REFHI REFLO (2) See Section 5.7. 23*I On-State Leakage Off-State Leakages samp samp samp Figure 7-1. MibADC Input Equivalent Circuit Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 73 (3) This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for example, the prescale settings. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 74 (1) 1 LSB = (AD – AD )/ 2 where n = 10 in 10-bit mode and 12 in 12-bit mode REFHI REFLO Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 75 – AD 2 where n=10 in 10-bit mode and 12 in 12-bit mode REFHI REFLO Figure 7-2. Differential Nonlinearity (DNL) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 76 – AD 2 where n=10 in 10-bit mode and 12 in 12-bit mode REFHI REFLO Figure 7-3. Integral Nonlinearity (INL) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 77 – AD 2 where n=10 in 10-bit mode and 12 in 12-bit mode REFHI REFLO Figure 7-4. Absolute Accuracy (Total) Error Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 78: General-Purpose Input/Output

    Internal pullup/pulldown allows unused I/O pins to be left unconnected For information on input and output timings see Section 5.11 Section 5.12 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 79: Enhanced High-End Timer (N2Het)

    The N2HET instructions PCNT and WCAP impose some timing constraints on the input signals. N2HETx Figure 7-5. N2HET Input Capture Timings Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 80 VCLK2 for input into the N2HET PIN_nDISABLE port. The PIN_nDISABLE port input source is selectable between the GIOA[5] and EQEPERR sources. This is achieved through the PINMMR9[1:0] bits. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 81 HTU DCP[2] N2HET HTUREQ[3] HTU DCP[3] N2HET HTUREQ[4] HTU DCP[4] N2HET HTUREQ[5] HTU DCP[5] N2HET HTUREQ[6] HTU DCP[6] N2HET HTUREQ[7] HTU DCP[7] Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 82: Controller Area Network (Dcan)

    Delay time, CANnRX pin to receive shift register d(CANnRX) (1) These values do not include rise/fall times of the output buffer. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 83: Local Interconnect Network Interface (Lin)

    – Synchronization Validation • programmable transmission rates with 7 fractional bits • Error detection • 2 Interrupt lines with priority encoding Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 84: Multibuffered / Standard Serial Peripheral Interface

    Up to 15 trigger sources are available which can be used by each transfer group. These trigger options are listed in Table 7-12. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 85 This way, a trigger condition can be generated either by selecting the GIOx pin as an output pin, or by driving the GIOx pin from an external trigger source. Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 86 (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 87 (clock polarity=1) SPISIMO Master Out Data Is Valid SPICSn SPIENAn Figure 7-7. SPI Master Mode Chip Select Timing (CLOCK PHASE = 0) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 88 (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). (6) C2TDELAY and T2CDELAY is programmed in the SPIDELAY register Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 89 (clock polarity=1) SPISIMO Master Out Data Is Valid SPICSn SPIENAn Figure 7-9. SPI Master Mode Chip Select Timing (CLOCK PHASE = 1) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 90 = 2t c(SPC)S c(VCLK) (6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 91 Figure 7-10. SPI Slave Mode External Timing (CLOCK PHASE = 0) SPICLK (clock polarity=0) SPICLK (clock polarity=1) SPIENAn SPICSn Figure 7-11. SPI Slave Mode Enable Timing (CLOCK PHASE = 0) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 92 ≥ 40 ns. c(SPC)S c(VCLK) (6) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17). Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 93 (clock polarity=1) SPIENAn SPICSn SPISOMI Slave Out Data Is Valid Figure 7-13. SPI Slave Mode Enable Timing (CLOCK PHASE = 1) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 94: Enhanced Quadrature Encoder (Eqep)

    PINMMR8[16] = 1 PINMMR8[16] = 0 and PINMMR8[17] = 1 eQEPS PINMMR8[24] = 1 PINMMR8[24] = 0 and PINMMR8[25] = 1 Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 95 Delay time, external clock to counter increment cycles d(CNTR)xin c(VCLK) Delay time, QEP input edge to position compare sync output cycles d(PCS-OUT)QEP c(VCLK) Peripheral Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 96: Device And Documentation Support

    Device Support 8.1.1 Development Support Texas Instruments (TI) offers an extensive line of development tools for the Hercules™ Safety generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.
  • Page 97 Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
  • Page 98 125 C Quality Designator: Quality Designator: Q1 = Automotive Shipping Options: Shipping Options: R = Tape and Reel Figure 8-1. Device Numbering Conventions Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 99: Documentation Support

    All other trademarks are the property of their respective owners. Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 100: Device Identification Code Register

    NO. OF BITS BIT LOCATION X Coord. on Wafer 0xFFFFFF7C[11:0] Y Coord. on Wafer 0xFFFFFF7C[23:12] Wafer # 0xFFFFFF7C[31:24] Lot # 0xFFFFFF80[23:0] Reserved 0xFFFFFF80[31:24] Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 101: Module Certifications

    SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 8.10 Module Certifications The following communications modules have received certification of adherence to a standard. Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 102 TMS570LS0432, TMS570LS0332 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 www.ti.com 8.10.1 DCAN Certification Figure 8-3. DCAN Certification Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 103 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 8.10.2 LIN Certifications 8.10.2.1 LIN Master Mode Figure 8-4. LIN Certification - Master Mode Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 104 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 www.ti.com 8.10.2.2 LIN Slave Mode - Fixed Baud Rate Figure 8-5. LIN Certification - Slave Mode - Fixed Baud Rate Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 105 SPNS186B – OCTOBER 2012 – REVISED JUNE 2015 8.10.2.3 LIN Slave Mode - Adaptive Baud Rate Figure 8-6. LIN Certification - Slave Mode - Adaptive Baud Rate Device and Documentation Support Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS0432 TMS570LS0332...
  • Page 106: Mechanical Packaging And Orderable Addendum

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Mechanical Packaging and Orderable Addendum Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links:...
  • Page 107 PACKAGE OPTION ADDENDUM www.ti.com 7-Aug-2015 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) TMS5700332APZQQ1 ACTIVE LQFP Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 TMS570LS &...
  • Page 108 PACKAGE OPTION ADDENDUM www.ti.com 7-Aug-2015 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
  • Page 109 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 110 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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