I2C Master Interrupt Mask (I2Cmimr) Register; I2C Master Raw Interrupt Status (I2Cmris) Register; I2C Master Interrupt Mask (I2Cmimr) Register Field Descriptions; I2C Master Raw Interrupt Status (I2Cmris) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
22.6.5 I2C Master Interrupt Mask (I2CMIMR), offset 0x010
The I2C Master Interrupt Mask (I2CMIMR) register controls whether a raw interrupt is promoted to a
controller interrupt. It is shown and described in the figure and table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-9. I2C Master Interrupt Mask (I2CMIMR) Register Field Descriptions
Bit Field
31-1 Reserved
0 IM
22.6.6 I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014
The I2C Master Raw Interrupt Status (I2CMRIS) register specifies whether an interrupt is pending. It is
shown and described in the figure and table below.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22-10. I2C Master Raw Interrupt Status (I2CMRIS) Register Field Descriptions
Bit Field
31-1 Reserved
0 RIS
1542
M3 Inter-Integrated Circuit (I2C) Interface
Figure 22-19. I2C Master Interrupt Mask (I2CMIMR) Register
Reserved
R-0
Value Description
Reserved
Interrupt Mask
0 The RIS interrupt is suppressed and not sent to the interrupt controller.
1 The master interrupt is sent to the interrupt controller when the RIS bit in the I2CMRIS register is
set.
Figure 22-20. I2C Master Raw Interrupt Status (I2CMRIS) Register
Reserved
R-0
Value Description
Reserved
Raw Interrupt Status. This bit is cleared by writing a 1 to the IC bit in the I2CMICR register.
0 No interrupt.
1 A master interrupt is pending.
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SPRUHE8E – October 2012 – Revised November 2019
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1 0
IM
R/W-0
1 0
RIS
R-0