Gpio Digital Enable (Gpioden) Register; Gpio Pull-Up Select (Gpiopur) Register Field Descriptions; Gpio Digital Enable (Gpioden) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

General-Purpose Input/Output (GPIO)
Table 4-16. GPIO Pull-Up Select (GPIOPUR) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 PUE
4.1.6.13 GPIO Digital Enable (GPIODEN) Register, offset 0x51C
NOTE: Pins configured as digital inputs are Schmitt-triggered.
The GPIODEN register is the digital enable register. By default, all GPIO signals are configured out of
reset to be undriven (tristate). Their digital function is disabled; they do not drive a logic value on the pin
and they do not allow the pin voltage into the GPIO receiver. To use the pin as a digital input or output
(either GPIO or alternate function), the corresponding GPIODEN bit must be set.
Important All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0,
GPIOPUR=0, and GPIOPCTL=0. A Power-On-Reset (POR) or asserting XRS puts the pins back to their
default state.
NOTE: The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware peripherals. Protection is provided for the NMI pin (PB7).
Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register, GPIO
Pull Up Select (GPIOPUR) register, GPIO Core Select (GPIOCSEL) register, and GPIO
Digital Enable (GPIODEN) register are not committed to storage unless the GPIO Lock
(GPIOLOCK) register has been unlocked and the appropriate bits of the GPIO Commit
(GPIOCR) register have been set.
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-17. GPIO Digital Enable (GPIODEN) Register Field Descriptions
Bit Field
31-8 Reserved
7-0 DEN
364
General-Purpose Input/Output (GPIO)
Value Description
Reserved
Pad Weak Pull-Up Enable
0 The corresponding pin is not affected.
1 The corresponding pin has a weak pull-up resistor.
The change is effective on the second clock cycle after the write if accessing GPIO via the APB
memory aperture. If using AHB access, the change is effective on the next clock cycle.
Figure 4-16. GPIO Digital Enable (GPIODEN) Register
R-0
Value Description
Reserved
Pad Weak Pull-Up Enable
0 The digital functions for the corresponding pin are disabled.
1 The digital functions for the corresponding pin are enabled.
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Reserved
R-0
8 7
SPRUHE8E – October 2012 – Revised November 2019
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DEN
R/W-0
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