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Host-Bus 8 and Host-Bus 16 modes are very configurable. The user has the ability to connect 1,2, or 4
external devices to the EPI signals, as well as control whether byte select signals are provided in HB16
mode. These capabilities depend on the configuration of the MODE field in the EPIHBnCFG register, the
CSCFG field and the CSCFGEXT bit in the EPIHBnCFGn register, and the BSEL bit in the EPIHB16CFG
register. The CSCFGEXT bit extends the chip select configuration possibilities by providing the most
significant bit of the CSCFG field. Refer to
can be programmed by the combination of the CSCFGEXT and CSCFG bits. Note that CSCFGEXT is the
most significant bit.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
If one of the dual-chip-select modes is selected (CSCFGEXT is 0x0 and CSCFG is 0x2 or 0x3 in the
EPIHBnCFGn register), both chip selects can share the peripheral, code, or the memory space, or one
chip select can use the peripheral space and the other can use the memory or code space.
In the EPIADDRMAP register, if the EPADR field is not 0x0, the ECADR field is 0x0, and the ERADR field
is 0x0, then the address specified by EPADR is used for both chip selects, with CS0 being asserted when
the MSB of the address range is 0 and CS1 being asserted when the MSB of the address range is 1.
If the ERADR field is not 0x0, the ECADR field is 0x0, and the EPADR field is 0x0, then the address
specified by ERADR is used for both chip selects, with the MSB performing the same delineation.
If both the EPADR and the ERADR are not 0x0, and the ECADR field is 0x0 and the EPI is configured for
dual-chip selects, then CS0 is asserted for either address range defined by EPADR and CS1 is asserted
for either address range defined by ERADR.
The two chip selects can also be shared between the code space and memory or peripheral space. If the
ECADR field is 0x1, ERADR field is 0x0, and the EPADR field is not 0x0, then CS0 is asserted for the
address range defined by ECADR and CS1 is asserted for either address range defined by EPADR.
If the ECADR field is 0x1, EPADR field is 0x0, and the ERADR field is not 0x0, then CS0 is asserted for
the address range defined by ECADR and CS1 is asserted for either address range defined by ERADR.
SPRUHE8E – October 2012 – Revised November 2019
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Table 17-2
for the possible ALE and chip select options that
Table 17-2. CSCFGEXT + CSCFG Encodings
ALE Configuration
EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the
address and data are muxed (MODE field in the EPIHB8CFG register is 0x0). The ALE
signal is used by an external latch to hold the address through the bus cycle.
CS Configuration
EPI0S30 is used as a Chip Select (CS). When using this mode, the address and data are
generally not muxed (MODE field in the EPIHB8CFG register is 0x1). However, if address
and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be
used to latch the address when CS is low.
Dual CS Configuration
EPI0S30 is used as CS0 and EPI0S27 is used as CS1. Whether CS0 or CS1 is asserted is
determined by the most significant address bit for a respective external address map. This
configuration can be used for a RAM bank split between 2 devices as well as when using
both an external RAM and an external peripheral.
ALE with Dual CS Configuration
EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1, and EPI0S26 is used as
CS0. Whether CS0 or CS1 is asserted is determined by the most significant address bit for a
respective external address map.
ALE with Single CS
Configuration EPI0S30 is used as address latch (ALE) and EPI0S27 is used as CS
Quad CS Configuration
EPI0S30 is used as CS0 and EPI0S27 is used as CS1. EPI0S34 is used as CS2 and
EPI0S33 is used as CS3
ALE with Quad CS Configuration
EPI0S30 is used as CS0 and EPI0S27 is used as CS1. EPI0S34 is used as CS2 and
EPI0S33 is used as CS3
Tri CS Configuration.
EPI0S30 is used CS0. EPI0S34 is used as CS2 and EPI0S33 is used as CS3
Copyright © 2012–2019, Texas Instruments Incorporated
Description
External Peripheral Interface (EPI)
Host Bus Mode
1237
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