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RAM Control Module Registers
Table 5-57. C28x Sx SHRAM Configuration Register 2 (CSxSRCR2) Field Descriptions
Bit
Field
31-27
Reserved
26
CPUWRPROTS7
25
DMAWRPROTS7
24
FETCHPROTS7
23-19
Reserved
18
CPUWRPROTS6
17
DMAWRPROTS6
16
FETCHPROTS6
15-11
Reserved
10
CPUWRPROTS5
9
DMAWRPROTS5
8
FETCHPROTS5
7-3
Reserved
2
CPUWRPROTS4
1
DMAWRPROTS4
0
FETCHPROTS4
512
Internal Memory
Value
Description
Reserved
CPU Write Protection S7
0
C28x CPU write allowed to S7 RAM block.
1
C28x CPU write not allowed to S7 RAM block.
DMA Write Protection S7
0
C28x DMA write allowed to S7 RAM block.
1
C28x DMA write not allowed to S7 RAM block.
CPU Fetch Protection S7
0
C28x CPU Fetch allowed from S7 RAM block.
1
C28x CPU Fetch not allowed from S7 RAM block.
Reserved
CPU Write Protection S6
0
C28x CPU write allowed to S6 RAM block.
1
C28x CPU write not allowed to S6 RAM block.
DMA Write Protection S6
0
C28x DMA write allowed to S6 RAM block.
1
C28x DMA write not allowed to S6 RAM block.
CPU Fetch Protection S6
0
C28x CPU Fetch allowed from S6 RAM block.
1
C28x CPU Fetch not allowed from S6 RAM block.
Reserved
CPU Write Protection S5
0
C28x CPU write allowed to S5 RAM block.
1
C28x CPU write not allowed to S5 RAM block.
DMA Write Protection S5
0
C28x DMA write allowed to S5 RAM block.
1
C28x DMA write not allowed to S5 RAM block.
CPU Fetch Protection S5
0
C28x CPU Fetch allowed from S5 RAM block.
1
C28x CPU Fetch not allowed from S5 RAM block.
Reserved
CPU Write Protection S4
0
C28x CPU write allowed to S4 RAM block.
1
C28x CPU write not allowed to S4 RAM block.
DMA Write Protection S4
0
C28x DMA write allowed to S4 RAM block.
1
C28x DMA write not allowed to S4 RAM block.
CPU Fetch Protection S4
0
C28x CPU Fetch allowed from S4 RAM block.
1
C28x CPU Fetch not allowed from S4 RAM block.
Copyright © 2012–2019, Texas Instruments Incorporated
SPRUHE8E – October 2012 – Revised November 2019
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