Table of Contents
Advertisement
Functional Description
A pending interrupt remains pending until one of the following:
•
The processor enters the ISR for the interrupt, changing the state of the interrupt from pending to
active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes
to inactive.
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the
state of the interrupt changes to pending and active. In this case, when the processor returns from
the ISR the state of the interrupt changes to pending, which might cause the processor to
immediately re-enter the ISR.If the interrupt signal is not pulsed while the processor is in the ISR,
when the processor returns from the ISR the state of the interrupt changes to inactive.
•
Software writes to the corresponding interrupt clear-pending register bit
– For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does
not change. Otherwise, the state of the interrupt changes to inactive.
– For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to
active, if the state was active and pending.
25.2.3 System Control Block (SCB)
The system control block (SCB) provides system implementation information and system control, including
configuration, control, and reporting of the system exceptions.
25.2.4 Memory Protection Unit (MPU)
NOTE: This feature is disabled on these devices.
The MPU divides the memory map into a number of regions and defines the location, size, access
permissions, and memory attributes of each region. The MPU supports independent attribute settings for
each region, overlapping regions, and export of memory attributes to the system.
The memory attributes affect the behavior of memory accesses to the region. The Cortex-M3 MPU defines
eight separate memory regions, 0-7, and a background region.
When memory regions overlap, a memory access is affected by the attributes of the region with the
highest number. For example, the attributes for region 7 take precedence over the attributes of any region
that overlaps region 7.
The background region has the same memory access attributes as the default memory map, but is
accessible from privileged software only.
The Cortex-M3 MPU memory map is unified, meaning that instruction accesses and data accesses have
the same region settings.
If a program accesses a memory location that is prohibited by the MPU, the processor generates a
memory management fault, causing a fault exception and possibly causing termination of the process in
an OS environment. In an OS environment, the kernel can update the MPU region setting dynamically
based on the process to be executed. Typically, an embedded OS uses the MPU for memory protection.
Configuration of MPU regions is based on memory types. See Memory Regions, Types and Attributes in
the Cortex-M3 Processor chapter for more information.
Table 25-2
shows the possible MPU region attributes. See
programming a microcontroller implementation.
Memory Type
Strongly Ordered
1638
Cortex-M3 Peripherals
Table 25-2. Memory Attributes Summary
Description
All accesses to Strongly Ordered memory occur in program
order.
Copyright © 2012–2019, Texas Instruments Incorporated
Section 25.2.4.2.1
for guidelines for
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
www.ti.com
Advertisement
Chapters
Table of Contents
