Lin Synchronization Field - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Functional Description
After detecting a Sync Break, the UART waits for the synchronization field. The first falling edge generates
an interrupt using the LME1RIS bit in the UARTRIS register, and the timer value is captured and stored in
the UARTLSS register (T1). On the fifth falling edge, a second interrupt is generated using the LME5RIS
bit in the UARTRIS register, and the timer value is captured again (T2). The actual baud rate can be
calculated using (T2-T1)/8, and the local baud rate should be adjusted as needed.
the synchronization field.
0 1 2 3 4 5
21.3.7 FIFO Operation
The UART has two 16-entry FIFOs; one for transmit and one for receive. Both FIFOs are accessed via the
UART Data (UARTDR) register. Read operations of the UARTDR register return a 12-bit value consisting
of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit FIFO.
Out of reset, both FIFOs are disabled and act as 1-byte-deep holding registers. The FIFOs are enabled by
setting the FEN bit in the UARTLCRH register.
FIFO status can be monitored via the UART Flag (UARTFR) register and the UART Receive Status
(UARTRSR) register. Hardware monitors empty, full and overrun conditions. The UARTFR register
contains empty and full flags (TXFE, TXFF, RXFE, and RXFF bits), and the UARTRSR register shows
overrun status via the OE bit.
The trigger points at which the FIFOs generate interrupts is controlled via the UART Interrupt FIFO Level
Select (UARTIFLS) register. Both FIFOs can be individually configured to trigger interrupts at different
levels. Available configurations include 1/8, 1/4, 1/2, 3/4, and 7/8. For example, if the 1/4 option is selected
for the receive FIFO, the UART generates a receive interrupt after 4 data bytes are received. Out of reset,
both FIFOs are configured to trigger an interrupt at the 1/2 mark.
21.3.8 Interrupts
The UART can generate interrupts when the following conditions are observed:
• Overrun Error
• Break Error
• Parity Error
• Framing Error
• Receive Timeout
• Transmit (when condition defined in the TXIFLSEL bit in the UARTIFLS register is met, or if the EOT
bit in UARTCTL is set, when the last bit of all transmitted data leaves the serializer)
• Receive (when condition defined in the RXIFLSEL bit in the UARTIFLS register is met)
All of the interrupt events are ORed together before being sent to the interrupt controller, so the UART can
only generate a single interrupt request to the controller at any given time. Software can service multiple
interrupt events in a single interrupt service routine by reading the UART Masked Interrupt Status
(UARTMIS) register.
The interrupt events that can trigger a controller-level interrupt are defined in the UART Interrupt Mask
(UARTIM) register by setting the corresponding IM bits. If interrupts are not used, the raw interrupt status
is always visible via the UART Raw Interrupt Status (UARTRIS).
1494
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 21-5. LIN Synchronization Field
Sync Break
6 7 8 9 10 11 12 13
Sync BreakDetect
Copyright © 2012–2019, Texas Instruments Incorporated
Synch Field
0 1 2 3 4 5
Edge 1
8 Tbit
SPRUHE8E – October 2012 – Revised November 2019
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Figure 21-5 illustrates
6 7 8
Edge 5