The Roles Of The Clock Divide-Down Values (Iccl And Icch); I2C Clock Low-Time Divider Register (I2Cclkl); I2C Clock High-Time Divider Register (I2Cclkh); I2C Clock Low-Time Divider Register (I2Cclkl) Field Description - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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determines the amount of time the signal is high.
Figure 14-22. The Roles of the Clock Divide-Down Values (ICCL and ICCH)
SCL
A As described in Section
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-13. I2C Clock Low-Time Divider Register (I2CCLKL) Field Description
Bit Field Value
15-0 ICCL
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14-14. I2C Clock High-Time Divider Register (I2CCLKH) Field Description
Bit Field Value
15-0 ICCH
14.5.7.1 Formula for the Master Clock Period
The period of the master clock (Tmst) is a multiple of the period of the module clock (Tmod):
T + T
mst mod
( IPSC ) 1 ) [ ( ICCL ) d ) ) ( ICCH ) d ) ]
T
+
mst
where d depends on the divide-down value IPSC, as shown in
Section 14.5.6.
SPRUHE8E – October 2012 – Revised November 2019
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High-time duration:
Tmod × (ICCH + d)
(A)
Low-time duration:
Tmod × (ICCL + d)
14.5.7.1, Tmod is the module clock period, and d is 5, 6, or 7.
Figure 14-23. I2C Clock Low-Time Divider Register (I2CCLKL)
Description
Clock low-time divide-down value. To produce the low-time duration of the master clock, the period
of the module clock is multiplied by (ICCL + d). d is 5, 6, or 7 as described in
Note: These bits must be set to a non-zero value for proper I2C clock operation.
Figure 14-24. I2C Clock High-Time Divider Register (I2CCLKH)
Description
Clock high-time divide-down value. To produce the high-time duration of the master clock, the
period of the module clock is multiplied by (ICCH + d). d is 5, 6, or 7 as described in
Section 14.5.7.1.
Note: These bits must be set to a non-zero value for proper I2C clock operation.
[( ICCL ) d ) ) ( ICCH ) d )]
I2C input clock frequency
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High-time duration:
Tmod × (ICCH + d)
(A)
Low-time duration:
Tmod × (ICCL + d)
(A)
ICCL
R/W-0
ICCH
R/W-0
Table 14-15. IPSC is described in
I2C Module Registers
(A)
Section 14.5.7.1.
C28 Inter-Integrated Circuit Module
0
0
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