Sci Tx Signals In Communications Mode - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Enhanced SCI Module Overview
TXENA
TXRDY
TX EMPTY
SCITXD pin
Notes:
1. Bit TXENA (SCICTL1, bit 1) goes high, enabling the transmitter to send data.
2. SCITXBUF is written to; thus, (1) the transmitter is no longer empty, and (2) TXRDY goes low.
3. The SCI transfers data to the shift register (TXSHF). The transmitter is ready for a second character
(TXRDY goes high), and it requests an interrupt (to enable an interrupt, bit TX INT ENA — SCICTL2,
bit 0 — must be set).
4. The program writes a second character to SCITXBUF after TXRDY goes high (item 3). (TXRDY goes
low again after the second character is written to SCITXBUF.)
5. Transmission of the first character is complete. Transfer of the second character to shift register
TXSHF begins.
6. Bit TXENA goes low to disable the transmitter; the SCI finishes transmitting the current character.
7. Transmission of the second character is complete; transmitter is empty and ready for new character.
13.1.1.8 SCI Port Interrupts
The SCI receiver and transmitter can be interrupt controlled. The SCICTL2 register has one flag bit
(TXRDY) that indicates active interrupt conditions, and the SCIRXST register has two interrupt flag bits
(RXRDY and BRKDT), plus the RX ERROR interrupt flag which is a logical OR of the FE, OE, BRKDT,
and PE conditions. The transmitter and receiver have separate interrupt-enable bits. When not enabled,
the interrupts are not asserted; however, the condition flags remain active, reflecting transmission and
receipt status.
The SCI has independent peripheral interrupt vectors for the receiver and transmitter. Peripheral interrupt
requests can be either high priority or low priority. This is indicated by the priority bits which are output
from the peripheral to the PIE controller. When both RX and TX interrupt requests are made at the same
priority level, the receiver always has higher priority than the transmitter, reducing the possibility of
receiver overrun.
The operation of peripheral interrupts is described in the peripheral interrupt expansion controller chapter
of the TMS320x2833x, 2823x System Control and Interrupts Peripheral Reference Guide (literature
number SPRUFB0
• If the RX/BK INT ENA bit (SCICTL2, bit 1) is set, the receiver peripheral interrupt request is asserted
when one of the following events occurs:
– The SCI receives a complete frame and transfers the data in the RXSHF register to the SCIRXBUF
register. This action sets the RXRDY flag (SCIRXST, bit 6) and initiates an interrupt.
– A break detect condition occurs (the SCIRXD is low for ten bit periods following a missing stop bit).
This action sets the BRKDT flag bit (SCIRXST, bit 5) and initiates an interrupt.
• If the TX INT ENA bit (SCICTL2.0) is set, the transmitter peripheral interrupt request is asserted
whenever the data in the SCITXBUF register is transferred to the TXSHF register, indicating that the
CPU can write to SCITXBUF; this action sets the TXRDY flag bit (SCICTL2, bit 7) and initiates an
interrupt.
1026
C28 Serial Communications Interface (SCI)
Figure 13-9. SCI TX Signals in Communications Mode
1
2 3 4
First Character
0 1 2
Start
Frame
.
Copyright © 2012–2019, Texas Instruments Incorporated
6
5
Second Character
0 1
Ad Pa Stop Start
SPRUHE8E – October 2012 – Revised November 2019
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2
Ad Pa Stop
Frame
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