Control Register (Control); Control Register (Control) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com

24.4.4.9 Control Register (CONTROL)

The CONTROL register controls the stack used and the privilege level for software execution when the
processor is in Thread mode. This register is only accessible in privileged mode.
Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL
register when in Handler mode. The exception entry and return mechanisms automatically update the
CONTROL register based on the EXC_RETURN value (see
running in Thread mode should use the process stack and the kernel and exception handlers should use
the main stack. By default, Thread mode uses MSP. To switch the stack pointer used in Thread mode to
PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex-M3 Instruction Set
Technical User's Manual, or perform an exception return to thread mode with the appropriate
EXC_RETURN value, as shown in
Note: When changing the stack pointer, software must use an ISB instruction immediately after the MSR
instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex-M3
Instruction Set Technical User's Manual.
31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
31-2 Reserved
0 ASP
TMPL
24.4.5 Exceptions and Interrupts
The processor supports interrupts and system exceptions. The processor and the Nested Vectored
Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of
software control. The processor uses handler mode to handle all exceptions except for reset. See
Section 24.7.7 for more information.
The NVIC registers control interrupt handling. See Nested Vectored Interrupt Controller (NVIC) in the
Cortex-M3 Peripherals chapter for more information.
24.4.6 Data Types
The processor supports 32-bit words, 16-bit halfwords, and 8-bit bytes. It also supports 64-bit data transfer
instructions. All instruction and data memory accesses are little endian. See
information.
24.5 Memory Model
This section describes the behavior of memory accesses and the bit-banding features. The memory map
for the controller is provided in the data manual.
The regions for SRAM and peripherals include bit-band regions. Bit-banding provides atomic operations to
bit data (see Section
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Table 24-18.
Figure 24-11. Control Register (CONTROL)
Reserved
R-0
Table 24-12. Control Register (CONTROL) Field Descriptions
Value Description
Reserved
Active Stack Pointer
0 MSP is the current stack pointer
1 PSP is the current stack pointer.
In Handler mode, this bit reads as zero and ignores writes. The processor updates this bit
automatically on exception return.
Thread mode privilege level
0 Only privileged software can be executed in thread mode.
1 Unprivileged software can be executed in thread mode.
24.6.4).
Copyright © 2012–2019, Texas Instruments Incorporated
Table 24-18). In an OS environment, threads
Section 24.6
Cortex-M3 Processor
Programming Model
1 0
ASP TMPL
R/W-0 R/W-0
for more
1615