Pie Vector Table In C-Boot Rom - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Vector Name (Number)

ITRAP or ILLEGAL

Note: Each of the functions in bold above are explained in detail further below in the document.

C-BootROM eventually enables PIE to handle IPC communication or commands from the master

subsystem during the boot process, as will be explained further below in this chapter. After PIE is enabled

the NMI, ITRAP and any enabled peripheral interrupt vectors are fetched from the PIE Vector table as

shown in table 0.13 below. C-Boot ROM enables only one PIE interrupt – MTOCIPCINT1, which is

interrupt line 1 in PIE GROUP 11. In other words C-Boot ROM enables PIE INT11.1 interrupt and enables

PIE during the boot process. All the remaining PIE interrupts are disabled, however PIE Vector table is

initialized with "cbrom_pie_isr_not_supported" handler for all the other PIE interrupts.

The table below only shows the interrupt and exception vectors that are fetched from C-Boot ROM

Please refer to the Control Subsystem PIE section in the System Control and Interrupts chapter for more

details on PIE. And PIE group vectors, the below table only shows how C-BootROM initialized PIE Vector

table during boot, user applications are free to disable PIE and re-initialize PIE as needed after the

application starts.

Vector Name (Number)

INT2 (2) – INT14 (14)

DLOGINT (15)

RTOSINT (16)

SPRUHE8E – October 2012 – Revised November 2019

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Table 6-13. C-Boot ROM CPU Vector Table (continued)

Vector Address or Location in

BootROM – When PIE is disabled

Table 6-14. PIE Vector Table in C-Boot ROM

Vector Address or Location – When PIE

is enabled, during boot process

0x00000D04 – 0x00000D1C

C-Boot ROM Description

Contents (Handler address)

cbrom_handle_nmi

cbrom_itrap_isr

Contents (Handler address)

cbrom_pie_isr_not_supported (Reset is

always fetched from 0x3FFFC0)

cbrom_pie_isr_not_supported

ROM Code and Peripheral Booting

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