Gpio Port B Mux 1 (Gpbmux1) Register; Gpio Port B Mux 1 (Gpbmux1) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

C28 General-Purpose Input/Output (GPIO)
Table 4-52. GPIO Port A MUX 2 (GPAMUX2) Register Field Descriptions (continued)
Bits Field
3-2 GPIO17
1-0 GPIO16
4.2.7.3

GPIO Port B MUX 1 (GPBMUX1) Register

The GPIO Port B MUX 1 (GPBMUX1) register is shown and described in the figure and table below.
31 30 29 28
GPIO47 GPIO46
R/W-0 R/W-0
15 14 13 12
GPIO39 GPIO38
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-53. GPIO Port B MUX 1 (GPBMUX1) Register Field Descriptions
Bit Field
31:30 GPIO47
29 - 28 GPIO45
27 - 26 GPIO45
25:24 GPIO44
406
General-Purpose Input/Output (GPIO)
Value Description
Configure the GPIO17 pin as:
00 GPIO17 - General purpose I/O 17 (default) (I/O)
01 SPISOMIA - SPI-A Slave output/Master input (I/O)
10 Reserved
11 Reserved
Configure the GPIO16 pin as:
00 GPIO16 - General purpose I/O 16 (default) (I/O)
01 SPISIMOA - SPI-A slave-in, master-out (I/O),
10 Reserved
11 Reserved
Figure 4-44. GPIO Port B MUX 1 (GPBMUX1) Register
27 26 25 24
GPIO45 GPIO44
R/W-0 R/W-0
11 10 9
GPIO37 GPIO36
R/W-0 R/W-0
Value Description
Configure this pin as:
00 GPIO 47 - general purpose I/O 47 (default)
01 Reserved
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 46 - general purpose I/O 46 (default)
01 Reserved
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 45 - general purpose I/O 45 (default)
01 Reserved
10 Reserved
11 Reserved
Configure this pin as:
00 GPIO 44 - general purpose I/O 44 (default)
01 Reserved
10 Reserved
11 Reserved
Copyright © 2012–2019, Texas Instruments Incorporated
(1)
23 22 21
GPIO43 GPIO42
R/W-0 R/W-0
8 7 6 5
GPIO35 GPIO34
R/W-0 R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
20 19 18 17
GPIO41 GPIO40
R/W-0 R/W-0
4 3 2 1
GPIO33 GPIO32
R/W-0 R/W-0
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