Priority Mask Register (Primask); Priority Mask Register (Primask) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Table 24-8. Program Status Register (PSR) Field Descriptions (continued)

24.4.4.6 Priority Mask Register (PRIMASK)

The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-

maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be

disabled when they might impact the timing of critical tasks. This register is only accessible in privileged

mode. The MSR and MRS instructions are used to access the PRIMASK register, and the CPS instruction

may be used to change the value of the PRIMASK register. See the Cortex-M3 Instruction Set Technical

User's Manual for more information on these instructions. For more information on exception priority

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

SPRUHE8E – October 2012 – Revised November 2019

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IPSR ISR Number. This field contains the exception type number of the current Interrupt Service

Routine (ISR).

Memory management fault

Reserved for Debug

Interrupt Vector 0

Interrupt Vector 1

Interrupt Vector 90

Section 24.7.2

for more information. The value of this field is only meaningful when accessing

PSR or IPSR.

Figure 24-8. Priority Mask Register (PRIMASK)

Table 24-9. Priority Mask Register (PRIMASK) Field Descriptions

Priority mask

Prevents the activation of all exceptions with configurable priority.

Programming Model

Cortex-M3 Processor

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