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eQEP Registers
Table 9-16. eQEP Watchdog Timer (QWDTMR) Register Field Descriptions
Bits
Name
15-0
QWDTMR
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-17. eQEP Watchdog Period (QWDPRD) Register Field Description
Bits
Name
15-0
QWDPRD
15
Reserved
7
6
PCR
PCO
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-18. eQEP Interrupt Enable(QEINT) Register Field Descriptions
Bits
Name
15-12
Reserved
11
UTO
10
IEL
9
SEL
8
PCM
7
PCR
6
PCO
884
C28 Enhanced QEP (eQEP) Module
Description
This register acts as time base for watch dog to detect motor stalls. When this timer value
matches with watch dog period value, watch dog timeout interrupt is generated. This register is
reset upon edge transition in quadrature-clock indicating the motion.
Figure 9-35. eQEP Watchdog Period (QWDPRD) Register
Value
Description
This register contains the time-out count for the eQEP peripheral watch dog timer.
When the watchdog timer value matches the watchdog period value, a watchdog
timeout interrupt is generated.
Figure 9-36. eQEP Interrupt Enable (QEINT) Register
12
R-0
5
4
PCU
WTO
R/W-0
R/W-0
Value
Description
0
Always write as 0
Unit time out interrupt enable
0
Interrupt is disabled
1
Interrupt is enabled
Index event latch interrupt enable
0
Interrupt is disabled
1
Interrupt is enabled
Strobe event latch interrupt enable
0
Interrupt is disabled
1
Interrupt is enabled
Position-compare match interrupt enable
0
Interrupt is disabled
1
Interrupt is enabled
Position-compare ready interrupt enable
0
Interrupt is disabled
1
Interrupt is enabled
Position counter overflow interrupt enable
Copyright © 2012–2019, Texas Instruments Incorporated
QWDPRD
R/W-0
11
10
UTO
IEL
R/W-0
R/W-0
3
2
QDC
QPE
R/W-0
R/W-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
0
9
8
SEL
PCM
R/W-0
R/W-0
1
0
PCE
Reserved
R/W-0
R-0
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