Uart Raw Interrupt Status (Uartris) Register; Uart Raw Interrupt Status (Uartris) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Register Descriptions
21.7.11 UART Raw Interrupt Status (UARTRIS), offset 0x03C
The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw
status value of the corresponding interrupt. A write has no effect.
31 30
23 22
15 14
LME5RIS LME1RIS
R-0 R-0
7 6
FERIS RTRIS
R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21-13. UART Raw Interrupt Status (UARTRIS) Register Field Descriptions
Bit Field
31-16 Reserved
15 LME5RIS
14 LME1RIS
13 LMSBRIS
12-11 Reserved
10 OERIS
9 BERIS
8 PERIS
7 FERIS
1510
M3 Universal Asynchronous Receivers/Transmitters (UARTs)
Figure 21-18. UART Raw Interrupt Status (UARTRIS) Register
29 28
21 20
13 12
LMSBRIS
R-0
5 4
TXRIS RXRIS
R-0 R-0
Value Description
Reserved
LIN Mode Edge 5 Raw Interrupt Status
This bit is cleared by writing a 1 to the LME5IC bit in the UARTICR register.
0 No interrupt
1 The timer value at the 5th falling edge of the LIN Sync Field has been captured.
LIN Mode Edge 1 Raw Interrupt Status
This bit is cleared by writing a 1 to the LME1IC bit in the UARTICR register.
0 No interrupt
1 The timer value at the 1st falling edge of the LIN Sync Field has been captured.
LIN Mode Sync Break Raw Interrupt Status
This bit is cleared by writing a 1 to the LMSBIC bit in the UARTICR register.
0 No interrupt
1 A LIN Sync Break has been detected.
Reserved
UART Overrun Error Raw Interrupt Status
This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.
0 No interrupt
1 An overrun error has occurred.
UART Break Error Raw Interrupt Status
This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.
0 No interrupt
1 A break error has occurred.
UART Parity Error Raw Interrupt Status
This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.
0 No interrupt
1 A parity error has occurred.
UART Framing Error Raw Interrupt Status
This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.
0 No interrupt
1 A framing error has occurred.
Copyright © 2012–2019, Texas Instruments Incorporated
27 26
Reserved
R-0
19 18
Reserved
R-0
11 10
Reserved OERIS
R-0
3
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
25 24
17 16
9 8
BERIS PERIS
R-0 R-0
0
Reserved
R-0
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