Test Data Out High Register (Fecc_Fouth_Test); Test Data Out Low Register (Fecc_Foutl_Test); Ecc Status Register (Fecc_Status); Test Data Out High Register (Fecc_Fouth_Test) Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

Flash Registers

5.4.2.16 Test Data Out High Register (FECC_FOUTH_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-118. Test Data Out High Register (FECC_FOUTH_TEST) Field Descriptions
Bit Field
31-0 DATAOUTH

5.4.2.17 Test Data Out Low Register (FECC_FOUTL_TEST)

31
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-119. Test Data Out Low Register (FECC_FOUTL_TEST) Field Descriptions
Bit Field
31-0 DATAOUTL

5.4.2.18 ECC Status Register (FECC_STATUS)

31
15
Reserved
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-120. ECC Status Register (FECC_STATUS) Field Descriptions
Bit Field
31-9 Reserved
8 CHK_ERR
7-2 ERR_POS
1 UNC_ERR
0 SINGLE_ERR
566
Internal Memory
Figure 5-110. Test Data Out High Register (FECC_FOUTH_TEST)
Value Description
High double word test data out. Holds bits 63:32 of the data out of the selected ECC block.
Figure 5-111. Test Data Out Low Register (FECC_FOUTL_TEST)
Value Description
Low double word test data out. Holds bits 31:0 of the data out of the selected ECC block.
Figure 5-112. ECC Status Register (FECC_STATUS)
9 8
CHK_ERR
R-0
Value Description
Reserved
Test mode ECC single bit error indicator. When 1, indicates that the single bit error is in
check bits. When 0, indicates that the single bit error is in data bits (If SINGLE_ERR field is
also set.
Test mode single bit error position. Holds the bit position where the single bit error occurred.
The position is interpreted depending on whether the CHK_ERR bit indicates a check bit or a
data bit. If CHK_ERR indicates a check bit error, the error position could range from 0 to 7,
or it could range from 0 to 63.
Test mode ECC double bit error. When 1 indicates that the ECC test resulted in an
uncorrectable bit error.
Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit
error.
Copyright © 2012–2019, Texas Instruments Incorporated
DATAOUTH
R-0
DATAOUTL
R-0
Reserved
R-0
7
ERR_POS
R-0
SPRUHE8E – October 2012 – Revised November 2019
www.ti.com
2 1 0
UNC_ERR SINGLE_ERR
R-0 R-0
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