Interrupts And Dma Events Generated By A Mcbsp; Mcbsp Sample Rate Generator - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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Frame Phases

In the preceding timing diagram

5. The McBSP shifts data bits from the transmit shift register(s) to the DX pin.

When activity is not properly timed, errors can occur. See the following topics for more details:

Overwrite in the Transmitter (

Underflow in the Transmitter

Unexpected Transmit Frame-Synchronization Pulse

15.3.7 Interrupts and DMA Events Generated by a McBSP

The McBSP sends notification of important events to the CPU and the DMA controller via the internal

signals shown in

Internal Signal

Each McBSP contains a sample rate generator (SRG) that can be programmed to generate an internal

data clock (CLKG) and an internal frame-synchronization signal (FSG). CLKG can be used for bit shifting

on the data receive (DR) pin and/or the data transmit (DX) pin. FSG can be used to initiate frame transfers

on DR and/or DX.

C28 Multichannel Buffered Serial Port (McBSP)

15-16), a 1-bit data delay is selected.

Table 15-3. Interrupts and DMA Events Generated by a McBSP

Receive interrupt

The McBSP can send a receive interrupt request to CPU based upon a selected condition in the receiver of

the McBSP (a condition selected by the RINTM bits of SPCR1).

Transmit interrupt

The McBSP can send a transmit interrupt request to CPU based upon a selected condition in the transmitter

of the McBSP (a condition selected by the XINTM bits of SPCR2).

Receive synchronization event

An REVT signal is sent to the DMA when data has been received in the data receive registers (DRRs).

Transmit synchronization event

An XEVT signal is sent to the DMA when the data transmit registers (DXRs) are ready to accept the next

serial word for transmission.

Figure 15-17

is a conceptual block diagram of the sample rate generator.

SPRUHE8E – October 2012 – Revised November 2019

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